Part Number Hot Search : 
21M3510 E1A102MR HA244 SFFD450M DTC144 H8FAMILY 2SD88 707EN
Product Description
Full Text Search
 

To Download S5L840F Datasheet File

  If you can't view the Datasheet, Please click here to try to view without PDF Reader .  
 
 


  Datasheet File OCR Text:
 CPAD-WALTZ(S5L840F)
Internet Audio Decoder for Flash Memory Media
Data Sheet
INTRODUCTION
S5L840F is a single chip digital audio player IC supporting various compressed audio format on Flash Memory Media. S5L840F provides 2Mbits of embedded NOR flash memory and 76Kbytes of SRAM requiring no external memory. A 16bit RISC processor (CALMRISC16TM) and 24bit MAC(MAC2424 TM) are provided as a CPU and DSP function.
FEATURES
* Supply voltage range: * * Supply Voltage (Core) : 1.8V Supply Voltage (IO) : 3.0V * * * * * * * * * IO DMA Supports SMC/MMC/SD/Memory Stic LCD Controller Interface 2 Channels of IIS IIC / SPDIF Output / UART / SPI USB1.1 5 channel 10bit ADC RTC GPIO
X-tal Oscillator: 32.768 KHz 16bit RISC(CalmRISC16) & 24bit MAC with 4KB of Instruction Cache 6KB of X Cache 6KB of Y Cache
*
2Mbit NOR Flash & 76KB SRAM
TYPICAL APPLICATION
* MP3/WMA/etc Player
ORDERING INFORMATION
Device S5L840F Package 128-TQFP-1414 Operating Temperature -40 C - +85 C
1
BLOCK DIAGRAM
76KB SRAM
2Mbit NOR-Flash
Timer RTC
10bit ADC GPIO LCD IF
Memory Controller
CalmADM3
WDT
4KB ROM
Interrupt Controller
3 2 b i t A H B P L U S
IO DMA
Clock Gen
UART
AHB to APB Bridge
3 2 b i t A P B
Memory stick I/F SD/MMC I/F SMC I/F
IIC(M/S) SPI IIS In IIS Out
USB1.1
SPDIF Out
CPAD-WALTZ
S5L840F
PIN CONFIGURATION
TEST2/ DEBUG TEST1 TEST_CLK TCK TMS TDI TDO EXHV VCC3F nERR/SDAT/ EINT4 / P1.6 SCLK/ EINT5 / P1.7 VDDF VSSF Xout Xin TEST0/TOOL EXHVEN LD0/P8.0 NRST_ADM PADVSS1 PADVDD1 INTVSS1 INTVDD1 LD1 / P8.1 LD2 / P8.2 LD3 / P8.3 LD4 / P8.4 LD5 / P8.5 LD6 / P8.6 LD7 / P8.7 Rx/P0.4 Tx/P0.5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97
LD_RE/P9.0 LD_WE/P9.1 LD_CS/P9.2 LD_REG/P9.3 LD_RST/P9.4 TACK/TACAP/P0.0 TAOUT/P0.1 TCCK/P0.2 SPDIF/P0.3 EINT6/P0.6/SDWP EINT7/P0.7/RBN PADVDD2 PADVSS2 INTVSS2 INTVDD2 EINT0/P2.0 EINT1/P2.1 EINT2/P2.2 EINT3/P2.3 DM DP VDDUSB VSSUSB IO0/P4.0 D1(SDC)/IO8/P5.0 IO1/P4.1 D0(SDC)/IO9/P5.1 IO2/P4.2 CLK_MMC_SDC/P3.0 CMD(SDC)/IO10/P5.2 IO3/P4.3 D3(SDC)/IO11/P5.3
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
AVREF AVSS ADC0 ADC1 ADC2 ADC3 ADC4 P10.4 P10.5 P10.6 P10.7 MOSI/P1.0 MISO/P1.1 SPISCK/P1.2 RUNST nRESET INTVSS5 INTVDD5 SCL/P1.3 SDA/P1.4 nSSI/P1.5 PADVDD4 PADVSS4 CLKSEL INTVSS6 INTVDD6 VDDPLL0 VSSPLL0 CP0 VDDPLL1 VSSPLL1 CP1
S5L840F
(Ver 35)
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
P10.3 P10.2 P10.1 P10.0 MCLK/P7.4 BCLK/P7.3 SD0/P7.2 INTVDD4 INTVSS4 LRCLK/P7.1 SD1/P7.0 nWP/P6.7 nWE/P6.6 ALE/P6.5 CLE/P6.4 nCE2/P6.3 nCE1/P6.2 nCE0/P6.1 nRE/P6.0 BS(MS)/IO15/P5.7 IO7/P4.7 D0(MS)/IO14/P5.6 IO6/P4.6 P3.1/CLK_MS IO13/P5.5 IO5/P4.5 D2(SDC)/IO12/P5.4 IO4/P4.4 INTVDD3 INTVSS3 PADVSS3 PADVDD3
3
PIN DESCRIPTION
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 I/O I I I I I I O B P B B P P O I I I B I P P P P B Pin Description DEBUG(internal F/F value dump) control Test mode Test clock JTAG clock. Pull-Up. JTAG mode selection. Pull-Up. JTAG input JTAG output Flash high voltage test Flash memory internal 3.3V Power. UART, GPIO UART, GPIO Flash memory internal 1.8V Power. GND for flash core Crystal oscillator signal (~100KHz) Crystal oscillator signal (~100KHz) BUS/Serial Controller Selection. Pull-Down Flash high volatge test enable. Pull-Down LCD I/F Adm reset. Pull-Up. Pad power GND Pad power VDD 3.3V Internal logic GND Internal logic Power VDD 1.8V LCD I/F
Pin Assignment TEST2/DEBUG TEST1 TEST_CLK(for debug) TCK TMS TDI TD0 EXHV VCC3F nERR/EINT4/P1.6 EINT5/P1.7 VDDF VSSF Xout Xin TEST0/TOOL_MODE EXHVEN LD0/P8.0 NTRST_ADM PADVSS1 PADVDD1 INTVSS1 INTVDD1 LD1/P8.1
CPAD-WALTZ
S5L840F
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
LD2/P8.2 LD3/P8.3 LD4/P8.4 LD5/P8.5 LD6/P8.6 LD7/P8.7 Rx/P0.4 Tx/P0.5 LD_RE/P9.0 LD_WE/P9.1 LD_CS/P9.2 LD_REG/P9.3 LD_RST/P9.4 TACK/TACAP/P0.0 TAOUT/P0.1 TCCK/P0.2 SPDIF/P0.3 EINT6/P0.6/SDWP EINT7/P0.7/RBN PADVDD2 PADVSS2 INTVSS2 INTVDD2 EINT0/P2.0 EINT1/P2.1 EINT2/P2.2
B B B B B B B B B B B B B B B B B B B P P P P B B B
LCD I/F LCD I/F LCD I/F LCD I/F LCD I/F LCD I/F INT, GPIO INT, GPIO LCD I/F LCD I/F LCD I/F LCD I/F LCD I/F Timer A, GPIO Timer A, GPIO Timer C, GPIO SPDIF, GPIO INT, GPIO, SDC_WP INT, GPIO, RBN(SMC) Pad power VDD 3.3V Pad power GND Internal logic GND Internal logic Power VDD 1.8V INT, GPIO INT, GPIO INT, GPIO
5
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76
EINT3/P2.3 DM DP VDDUSB VSSUSB IO0/P4.0 D1(SDC)/IO8/P5.0 IO1/P4.1 D0(SDC)/IO9/P5.1 IO2/P4.2 CLK_MMC_SDC/P3.0 CMD(SDC)/IO10/P5.2 IO3/P4.3 D3(SDC)/IO11/P5.3 PADVDD3 PADVSS3 INTVSS3 INTVDD3 IO4/P4.4 D2(SDC)/IO12/P5.4 IO5/P4.5 IO13/P5.5 P3.1/CLK_MS IO6/P4.6 D0(MS)/IO14/P5.6 IO7/P4.7
B B B P P B B B B B B B B B P P P P B B B B B B B B
INT, GPIO USB transceive/receive port USB transceive/receive port USB Power 3.3V USB Ground IO0 for SMC /Debug scan in IO8 for SMC, D0 for SDC IO1 for SMC IO9 for SMC, D1 for SDC IO2 for SMC CLK for MMC/SDC IO10 for SMC, CMD/RESP for SDC IO3 for SMC IO11 for SMC, D3 for SDC Pad power VDD 3.3V Pad power GND Internal logic GND Internal logic Power VDD 1.8V IO4 for SMC IO12 for SMC, D2 for SDC IO5 for SMC IO13 for SMC GPIO, CLK for MS IO6 for SMC IO14 for SMC, D0 for MS IO7 for SMC
CPAD-WALTZ
S5L840F
77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102
BS(MS)/IO15/P5.7 nRE/P6.0 nCE0/P6.1 nCE1/P6.2 nCE2/P6.3 CLE/P6.4 ALE/P6.5 nWE/P6.6 nWP/P6.7 SD1/P7.0 LRCLK/P7.1 INTVSS4 INTVDD4 SD0/P7.2 BCLK/P7.3 MCLK/P7.4 P10.0 P10.1 P10.2 P10.3 AVREF AVSS ADC0 ADC1 ADC2 ADC3
B B B B B B B B B B B P P B B B B B B B P P I I I I
IO15 for SMC, BS for MS SMC control SMC control SMC control SMC control SMC control SMC control SMC control /Debug scan out SMC control Serial Data In for IIS Left-Right Clock for IIS Internal logic GND Internal logic Power VDD 1.8V Serial Data Out for IIS Bit Clock for IIS Over-sampling Clock for IIS GPIO GPIO GPIO GPIO ADC VREF,AVDD33A1,AVDD33A2 . 3.3V Power ADC analog GND. avss33a1,avbb33a1,avss33a2 ADC ADC ADC ADC
7
103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
ADC4 P10.4 P10.5 P10.6 P10.7 MOSI/P1.0/tclk0 MISO/P1.1/tclk1 SPISCK/P1.2 RUNST nRESET INTVSS5 INTVDD5 SCL/P1.3 SDA/P1.4 nSSI/P1.5 PADVDD4 PADVSS4 CLKSEL INTVSS6 INTVDD6 VDDPLL0 VSSPLL0 CP0 VDDPLL1 VSSPLL1 CP1
I B B B B B B B B I P P B B B P P I P P P P O P P O
ADC GPIO GPIO GPIO GPIO SPI, GPIO, TCLK0(not open) SPI, GPIO, TCLK1(not open) SPI, GPIO JTAG RUNID / TEST mode select System RESET. Pull-Up. Internal logic GND Internal logic Power VDD 1.8V IIC, GPIO IIC, GPIO SPI, IIC, UART Pad power VDD 3.3V Pad power GND Clock selection signal. Pull-Up. Internal logic GND Internal logic Power VDD 1.8V PLL Power supply VDD 1.8V PLL GND Low pass filter circuit for pll0 PLL Power supply VDD 1.8V PLL GND Low pass filter circuit for pll1
CPAD-WALTZ
S5L840F
ABSOLUTE MAXIMUM RATINGS
Characteristic Supply Voltage Input Voltage Storage Temperature Range Symbol VDD VIN Tstg Value 3.8 6.5 -65-150 Unit V V C
ELECTRICAL CHARACTERISTICS
Recommended Operating Conditions Characteristic Supply Voltage Operating Temperature Range Symbol VDD Topr Value 1.65~1.95(Core), 2.7~3.3(IO) -40-85 Unit V C
DC Characteristics (Ta = 25C, VDD(IO) = 3.3V, Unless otherwise specified) Symbol VIH VIL VT VT+ VTVOH VOL IOZ Characteristic High level input voltage Low level input voltage Switching threshold Schmitt trigger, positive -going threshold Schmitt trigger, negative-going threshold High level output voltage Low level output voltage Tri-state output leakage current Test Conditions - - CMOS CMOS IOH = -2mA IOL = 2mA Vout = Vss or GND 0.8 2.4 - -10 - - - - 0.4 10 Min 2.0 - Typ - - 1.4 2.0 Max - 0.8 Unit V V V V V V V A
NOTES:
9
PACKAGE DIMENSIONS
Low-Power & High-Performance RISC Core
CalmRISC16 Technical Reference Manual
MCU Team LSI Division System LSI Business Samsung Electronics Co.
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
1. Introduction
1.1 Feature
The main features of CalmRISC16, a 16-bit embedded RISC MCU core, are high performance, low power consumption, and efficient coprocessor interface. It can operate up to 100MHz, and consumes 100A/MHz @3.3V. When operating with MAC2424, a 24-bit fixed point DSP coprocessor, CalmRISC16 can operate up to 80MHz. Through efficient coprocessor interface, CalmRISC16 provides a powerful and flexible MCU+DSP solution. The following gives brief summary of main features of CalmRISC16. H/W Feature Power consumption : 100A per MHz @3.3V, 0.35 process Maximum frequency : 100MHz @3.3V 0.78 mm2 die size Architecture Harvard RISC architecture 5-Stage pipeline Registers Sixteen 16-bit general registers Eight 6-bit extension registers 22-bit Program Counter (PC) 16-bit Status Register (SR) Seven saved registers for interrupts. Instruction Set 16-bit instruction width for 1-word instructions 32-bit instruction width for 2-word instructions Load/Store instruction architecture Delayed branch support C-language/OS support Bit operation for I/O process Instruction Execution Time One instruction/cycle for basic instructions Address Space 4M byte for Program Memory 4M byte for Data Memory
MCU Team LSI Division System LSI Business
-2-
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
1.2. Registers
In CalmRISC16 there are sixteen 16-bit general registers, eight 6-bit extension registers, a 16-bit Status Register(SR), a program counter (PC), and seven saved registers. General Registers & Extension Registers The following figure shows the structure of the general registers and the extension registers.
R0 R1 Registers for Byte
PC SPC_FIQ SPC_IRQ SR SSR_FIQ SSR_IRQ SSR_SWI
R7 E8 E9 R8 R9
Address Registers
E14 E15
R14 R15
Link Register Stack Pointer
Register Structure in CalmRISC16
The general registers (from R0 to R15) can be either a source register or a destination register for almost all ALU operations, and can be used as an index register for memory load/store instructions (e.g., LDW R3, @[A8+R2]). The 6-bit extension registers (from E8 to E15) are used to form a 22-bit address register (from A8 to A15) by concatenating with a general register (from R8 to R15). The address registers are used to generate 22-bit program and data addresses. Special Registers The special registers consist of 16-bit SR (Status Register), 22-bit PC (Program Counter), and saved registers for IRQ(interrupt), FIQ(fast interrupt), and SWI(software interrupt). When IRQ interrupt occurs, the most significant 6 bits of the return address are saved in SPCH_IRQ, the least significant 16 bits of
MCU Team LSI Division System LSI Business -3April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
the return address are saved in SPCL_IRQ, and the status register is saved in SSR_IRQ. When FIQ interrupt occurs, the most significant 6 bits of the return address are saved in SPCH_FIQ, the least significant 16 bits of the return address are saved in SPCL_FIQ, and the status register is saved in SSR_FIQ. When a SWI instruction is executed, the return address is saved in A14 register (E14 concatenated with R14), and the status register is saved in SSR_SWI. The least significant bit of PC, SPCL_IRQ and SPCL_FIQ is read only and its value is always 0. The 16-bit register SR has the following format. 15 T 8 7 PM Z1 Z0 V TE IE 0 FE
FE : FIQ enable bit, FIQ is enabled when FE is set. IE : IRQ enable bit, IRQ is enabled when IE is set. TE : TRQ enable bit, Trace is enabled when TE is set. V : overflow flag, set/clear accordingly when arithmetic instructions are executed. Z0 : zero flag of R6, set when R6 equals zero and used as the branch condition when BNZD instruction with R6 is executed. Z1 : zero flag of R7, set when R7 equals zero and used as the branch condition when BNZD instruction with R7 is executed. PM : privilege mode bit. PM = 1 for privilege mode and PM = 0 for user mode T : true flag, set/clear as a result of an ALU operation. FE, IE, TE, and PM bits can be modified only when PM = 1 (privilege mode). The only way to change from user mode to privilege mode is via interrupts including SWI instructions. The reserved bit of SR (from bit 7 to bit 14) can be used for other purposes without any notice. Hence programmers should not depend on the value of the reserved bits in their programming. The reserved bits are read as 0 value.
1.3. Pipeline Structure
CalmRISC16 has a 5-stage pipeline architecture. It takes 5 cycles for an instruction to do its operation. In a pipeline architecture, instructions are executed overlapped, hence the throughput is one instruction per cycle. Due to data dependency, control dependency, and 2 word instructions, the throughput is about 1.2 on the average. The following diagram depicts the 5-stage pipeline structure.
IF
ID
EX
MEM
WB
In the first stage, which is called IF (Instruction Fetch) stage, an instruction is fetched from program
MCU Team LSI Division System LSI Business -4April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
memory. In the second stage, which is called ID (Instruction Decoding) stage, the fetched instruction is decoded, and the appropriate operands, if any, for ALU operation are prepared. In the case of branch or jump instructions, the target address is calculated in ID stage. In the third stage, which is called EX (Execution) stage, ALU operation and data address calculation are executed. In the fourth stage, which is called MEM (Memory) stage, data transfer from/to data memory or program memory is executed. In the fifth stage, which is called WB (Write Back) stage, a write-back to register file can be executed. The following figure shows an example of pipeline progress when 3 consecutive instructions are executed.
I1 : ADD R0, 3 I2 : ADD R1, R0 I3 : LD R2, R0
IF
ID IF
EX ID IF
MEM EX ID
WB MEM EX WB MEM WB
In the above example, the instruction I2 needs the result of the instruction I1 before I1 completes. To resolve this problem, the EX stage result of I1 is forwarded to ID stage of I2. Similar forwarding mechanism occurs from MEM stage of I1 to ID stage of I3. The pipeline cannot progress (called a pipeline stall) due to a data dependency, a control dependency, or a resource conflict. When a source operand of an ALU instruction is from a register, which is loaded from memory in the previous instruction, 1 cycle of pipeline stall occurs (called load stall). Such load stalls can be avoided by smart reordering of the instruction sequences. CalmRISC16 has 2 classes of branch instructions, those with a delay slot and without a delay slot. Non-delay slot branch instructions incurs a 1 cycle pipeline stall if the branch is taken, due to a control dependency. For branch instructions with a delay slot, no cycle waste is incurred if the delay slot is filled with a useful instruction (or non NOP instruction). Pipeline stalls due to resource conflicts occurs when two different instructions access at the same cycle the same resource such as the data memory and the program memory. LDC (data load from program memory) instruction causes a resource conflict on the program memory. Bit operations such as BITR and BITS (read-modify-write instructions) cause a resource conflict on the data memory.
1.4 Interrupts
In CalmRISC16, there are five interrupts: RESET, FIQ, IRQ, TRQ, SWI. The RESET, FIQ, and IRQ interrupts correspond to external requests. TRQ and SWI interrupts are initiated by an instruction (therefore, in a deterministic way). The following table shows a summary of interrupts.
Name RESET FIQ
Priority 1 3
Address 000000h 000002h
MCU Team LSI Division System LSI Business
Description Hardware Reset Fast Interrupt Request
-5April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual 000004h 000006h 000008h ~ 0000feh Interrupt Request Trace Request Software Interrupt
IRQ TRQ SWI
5 2 4
When nRES (an input pin CalmRISC16 core) signal is released (transition from 0 to 1), "JMP addr:22" is automatically executed by CalmRISC16. Among the 22-bit address addr:22, the most significant 6 bits are forced to 0, and the least significant 16 bits are the contents of 000000h (i.e., reset vector address) of the program memory. In other words, "JMP {6'h001, PM[000000h]}" instruction is forced to the pipeline. The initial value of PM bit is 1 (that is, in privilege mode) and the initial values of other bits in SR register are 0. All other registers are not initialized (i.e., unknown). When nFIQ (an input pin CalmRISC16 core) signal is active (transition from 1 to 0), "JMP addr:22" instruction is automatically executed by CalmRISC16. The address of FIQ interrupt service routine is in 000002h (i.e., FIQ vector address) of the program memory (i.e., "JMP {6'h00, PM[000002h]}"). The return address is saved in {SPCH_FIQ, SPCL_FIQ} register pair, and the SR value is saved in SSR_FIQ register. PM bit is set. FE, IE, and TE bits are cleared. When RET_FIQ instruction is executed, SR value is restored from SSR_FIQ, and the return address is restored into PC from {SPCH_FIQ, SPCL_FIQ}. When nIRQ signal (an input pin CalmRISC16 core) is active (transition from 1 to 0), "JMP {6'h00, PM[000004h]}" instruction is forced to the instruction pipeline. The return address is saved in {SPCH_IRQ, SPCL_IRQ} register pair, and the SR value is saved in SSR_IRQ register. PM bit is set. IE and TE bits are cleared. When RET_IRQ instruction is executed, SR value is restored from SSR_IRQ, and return address is restored to PC from {SPCH_IRQ, SPCL_IRQ}. When TE bit is set, TRQ interrupt happens and "JMP {6'h00, PM[000006h]}" instruction is executed right after each instruction is executed. TRQ interrupt uses the saved registers of IRQ(that is, {SPCH_IRQ, SPCL_IRQ} register pair and SSR_IRQ) to save the return address and SR, respectively. PM bit is set. IE, TE bits are cleared. When "SWI imm:62" instruction is executed, the return address is saved in the register A14, and the value of SR is saved in SSR_SWI. Then the program sequence jumps to the address (imm:6 * 4). PM bit is set. IE and TE bits are cleared. "SWI 0" and "SWI 1" are prohibited because the addresses are reserved for other interrupts. When RET_SWI instruction is executed, SR is restored from SSR_SWI, and the return address is restored to PC from A14.
1.5 Memory Formats
1 2
6'h00 is defined as 00 (or zero) in 6 bits imm:6 is defined as 6-bit immediate number
MCU Team LSI Division System LSI Business -6April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
CalmRISC16 adopts a big endian memory format. In a big endian memory format, the most significant byte of word data is stored at an even address, and the least significant byte is stored at an odd address. For example let us assume that the word data "1234h" is stored at the address 100h. Then the higher byte "12h" is stored at the address 100h, and the lower byte "34h" is stored at the address 101h. When the 22-bit data "123456h" is stored at the address 100h by "LDW @An, Ai" instruction, "00h" is at the address 100h, "12h" is at the address 101h, "34h" is at the address 102h, and "56h" is at the address 103h.
1.6 Signal Description
Name PA[20:0] PD[15:0] nPMCS nLDC DA[21:0] DI[15:0] DO[15:0] nDMCSH nDMCSL DMWR nDME nRES nFIQ nIRQ nEXPACK nWAIT nSYSID MCLK ECLK ICLK nCOPID nCLDID CLDWR Direction O I O O O I O O O O O I I I O I O I O O O O O Description Program Memory Address, equivalent to PC[21:1] Program Data Program Memory Chip Selection Data load from program memory indicator Data Memory Address DA[4:0] is shared with SYS and CLD instructions Input from Data Memory, Input from coprocessor for CLD instruction. Output to Data Memory, Output to coprocessor for CLD instruction. Chip Selection for Higher Byte Data Memory Chip Selection for Lower Byte Data Memory Data Memory Write, 1 means transfer from Core to Memory Data Bus Enable Signal. Hardware Reset Fast Interrupt Request Interrupt Request Exception Acknowledge Wait signal, core is stopped when active. SYS instruction indicator Main Clock Input Early Clock Output Clock Output Coprocessor instruction indicator Coprocessor Load instruction indicator Write to Coprocessor indicator
MCU Team LSI Division System LSI Business -7April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual Instruction to coprocessor, 13-bit immediate field in COP instruction. External Conditions from coprocessor or peripherals. Software break indicator Break Acknowledge Break Mode, indicates core state when core breaks. Break Request Global interrupt disable, when active, all interrupt is disabled. Indicates program memory access is permitted. Indicates current program memory access is not complete. Indicates data memory access is permitted. Indicates current data memory access is not complete. Signal asking for data bus permission. Privilege Mode Indicator Indicates that coprocessor may use data bus. Coprocessor indicates that coprocessor pipeline stall occurs. Coprocessor indicates that coprocessor instruction is multiple word. Indicates that the next program address is sequential. If it is 1, PC value is not incremented when sequential execution. Clock output to coprocessor
COPIR[12:0] EC[3:0] nBRK nBKACK BKMODE[2:0] BKREQ nGIDIS PDGRANT PDWAIT DBGRANT DBWAIT DBREQ PMODE CGRANT CSTALL CMW nSEQ nINCPC CCLK
O I O O O I I I I I I O O O I I O I O
2. Instructions
2.1. ALU instructions
In operations between a 16-bit general register and an immediate value, the immediate value is zeroextended to 16-bit. The following figure shows an example of 7-bit immediate numbers.
6 imm:7 15 '0' 7
0
7-bits immediate
7-bits immediate
In operations between a 22-bit register and an immediate value, the immediate value is zero-extended to
MCU Team LSI Division System LSI Business -8April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
22-bit. In operations between a 22-bit register and a 16-bit register, the 16-bit register is zero-extended to 22-bit. The overflow flag in a 16-bit arithmetic operation is saved to V flag in SR register. ALU instructions are classified into 3 classes as follows. ALUop Register, Immediate ALUop Register, Register ALUop Register
ALUop Register, Immediate ADD/ADC/SUB/SBC/AND/OR/XOR/TST/CMP/CMPU Rn, #imm:16 The instructions perform an ALU operation of which source operands are a 16-bit general register Rn and a 16-bit immediate value. In the instructions TST/CMP/CMPU, only T flag is updated accordingly as the result. In the instructions ADD/ADC/SUB/SBC, the value of T flag is the carry flag of the operations, and the value of V flag indicates whether overflow or underflow occurs. In the instructions AND/OR/XOR/TST, the value of T flag indicates whether the result is zero (T=1). "CMP {GT|GE|EQ}, Rn, #imm:163" instructions are for signed comparison operations (GT for greater than, GE for greater than or equal to and EQ for equal to), and "CMPU {GT|GE}, Rn, #imm:16" instructions are for unsigned comparison operations. ADD/SUB An, #imm:16 The immediate value is zero-extended to 22-bit value. No flag update occurs. ADD/SUB Rn, #imm:7 The immediate value is zero-extended to 16-bit value. T flag is updated to the carry of the operation. V flag is updated. AND/OR/XOR/TST R0, #imm:8 The immediate value is zero-extended to 16-bit value. T flag indicates whether the lower 8-bit of the logical operation result is zero. CMP EQ, Rn, #imm:8 The immediate value is zero-extended to 16-bit value. Rn is restricted to R0 to R7. T flag is updated as the result of the instruction.
3
imm:16 is defined as a 16-bit immediate number
MCU Team LSI Division System LSI Business -9April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
CMP GE, Rn, #imm:6 The immediate value is zero-extended to 16-bit value. The instruction is for signed compare. T flag is updated as the result of the instruction. ADD/SUB An, #imm:5 The immediate value is zero-extended to 22-bit value. No flag is updated.
ALUop Register, Register ADD/SUB/ADC/SBC/AND/OR/XOR/TST/CMP/CMPU Rn, Ri The instructions perform an ALU operation of which source operands are a pair of 16-bit general registers. In the instructions TST/CMP/CMPU, only T flag is updated as the result. In the instructions ADD/ADC/SUB/SBC, the value of T flag is the carry of the operations, and the value of V flag indicates whether overflow or underflow occurs. In the instructions AND/OR/XOR/TST, the value of T flag indicates whether the result is zero. "CMP {GT|GE|EQ}, Rn, Ri" instructions are for signed comparison, and "CMPU {GT|GE}, Rn, Ri" instructions are for unsigned comparison. ADD/SUB An, Ri 16-bit general register Ri is zero-extended to 22-bit value. The result is saved in the 22-bit register An. No flag update occurs. CMP EQ, An, Ai The instruction compares two 22-bit registers. MUL {SS|SU|US|UU}, Rn, Ri The general registers Rn and Ri can be one of R0 to R7. The instruction multiplies the lower byte of Rn and the lower byte of Ri, and the 16-bit result is saved in Rn. The optional field, SS, SU, US, and UU, indicates whether the source operands are signed value or unsigned value. The first letter of the two letter qualifiers corresponds to Rn, and the second corresponds to Ri. For example, in the instruction "MUL SU, R0, R1", the 8-bit signed value in the lower byte of R0 and the 8-bit unsigned value in the lower byte of R1 are multiplied, and the 16-bit result is saved in R0. RR/RL/RRC/SR/SRA/SLB/SRB/DT/INCC/DECC/COM/COM2/COMC/EXT Rn For "DT Rn"(Decrement and Test) and "COM Rn"(Complement) instructions, T flag indicates whether the result is zero. In the instruction of "EXT Rn"(Sign Extend), no flag update occurs. In all other instructions, carry-out of the operation is transferred to T flag. In the instruction of DT, INCC, and DECC,
MCU Team LSI Division System LSI Business - 10 April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
V flag indicates whether overflow or underflow occurs.
2.2. Load instructions
"Load instructions" move data from register/memory/immediate to register/memory. When the
destination is a memory location, only general registers and extension registers can be the source. We can classify "Load instructions" into the following 4 classes. LD Register, Register LD Register, Immediate LD Data Memory, Register / LD Register, Data Memory LD Register, Program Memory LD Register, Register LD Rn, Ri / LD An, Ai The instructions move 16-bit or 22-bit data from the source register to the destination register. When the destination register is R6/R7, the zero flag Z0/Z1 is updated. In all other cases, no flag update occurs. LD Rn, Ei / LD En, Ri In the instruction "LD Rn, Ei", the 6-bit data in Ei is zero-extended to 16-bit data, and then transferred to Rn. When the destination register is R6/R7, the zero flag Z0/Z1 is updated. In the instruction "LD En, Ri", least significant 6 bits of Ri are transferred to En. Rn/Ri is one of the registers from R0 to R7. LD R0, SPR / LD SPR, R0 SPR : SR, SPCL_FIQ, SPCH_FIQ, SSR_FIQ, SPCL_IRQ, SPCH_IRQ, SSR_IRQ, SSR_SWI The instructions transfer data between SPR (Special Purpose Registers) and R0. No flag update occurs except the case that the destination register is SR. LD An, PC The instruction moves the value of (PC+4) to An. LD Register, Data Memory / LD Data Memory, Register LDW Rn, @[SP+edisp:9] / LDW @[SP+edisp:9], Rn The instructions transfer 16-bit data between a general register Rn and the memory location at the address of (SP+edisp:9). Note SP is another name of A15. edisp:9 is an even positive displacement from 0 to 510.
MCU Team LSI Division System LSI Business - 11 April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
edisp:9 is encoded into an 8-bit displacement value in the instruction map because the LSB is always 0. When the address is calculated, the 8-bit displacement field is shifted to the left by one bit, and then the result is added to the value of SP. Even if the address might be specified as odd in assembly mnemonic, the LSB of the address should be truncated to zero for word alignment. LDW Rn, @[Ai+edisp:5] / LDW @[Ai+edisp:5], Rn The instructions transfer 16-bit data between a general register Rn and the memory location at the address of (Ai+edisp:5). edisp:5 is an even positive displacement from 0 to 30. edisp:5 is encoded into an 4-bit displacement value in the instruction map because the LSB is always 0. When the address is calculated, the 4-bit displacement field is shifted to the left by one bit, and then the result is added to the value of Ai. Even if the address might be specified as odd in assembly mnemonic, the LSB of the address should be truncated to zero for word alignment. LDW Rn, @[Ai+disp:16] / LDW @[Ai+disp:16], Rn The instructions transfer 16-bit data between a general register Rn and the memory location at the address of (Ai+disp:16). disp:16 is an positive displacement from 0 to FFFFh. If the address is odd, the LSB of the address is set to zero for word alignment. LDW Rn, @[Ai+Rj] / LDW @[Ai+Rj], Rn The instructions transfer 16-bit data between a general register Rn and the memory location at the address of (Ai+Rj). The value of Rj is zero-extended to 22-bit value. If the address is odd, the LSB of the address is set to zero for word alignment. LDW An, @[Ai+edisp:5] / LDW @[Ai+edisp:5], An The instructions transfer 22-bit data between an address register An and the memory location at the address of (Ai+edisp:5). edisp:5 is an even positive displacement from 0 to 30. edisp:5 is encoded into an 4-bit displacement value in the instruction map because the LSB is always 0. When the address is calculated, the 4-bit displacement field is shifted to the left by one bit, and then the result is added to the value of Ai. Even if the address might be specified as odd in assembly mnemonic, the LSB of the address should be truncated to zero for word alignment. LDW An, @[Ai+disp:16] / LDW @[Ai+disp:16], An The instructions transfer 22-bit data between an address register An and the memory location at the address of (Ai+disp:16). disp:16 is an positive displacement from 0 to FFFFh. If the address is odd, the LSB of the address is set to zero for word alignment. LDW An, @[Ai+Rj] / LDW @[Ai+Rj], An
MCU Team LSI Division System LSI Business - 12 April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
The instructions transfer 22-bit data between an address register An and the memory location at the address of (Ai+Rj). The value of Rj is zero-extended to 22-bit value. If the address is odd, the LSB of the address is set to zero for word alignment. PUSH Rn/PUSH Rn, Rm/PUSH An/ PUSH An, Am The instruction "PUSH Rn" transfers 16-bit data from the register Rn to the memory location at the address of SP, and then increments the value of SP by 2. The register Rn should not be R15. The operation of "PUSH R15" is undefined. The instruction "PUSH Rn, Rm" pushes Rn and then Rm. The registers Rn and Rm should not be the same. The registers Rn and Rm should not be R15. The instruction "PUSH An" pushes Rn and then En. When the extension register En is pushed, the value of En is zeroextended to 16-bit data. The register An should not be A15. The instruction "PUSH An, Am" pushes An and then Am. The registers An and Am should not be the same POP Rn/POP Rn, Rm/POP An/ POP An, Am The instruction "POP Rn" decrements the value of SP by 2, and then transfers 16-bit data to the register Rn from the memory location at the address of SP. The register Rn should not be R15. The operation of "POP R15" is undefined. The instruction "POP Rn, Rm" pops Rn and then Rm. The registers Rn and Rm should not be the same. The registers Rn and Rm should not be R15. The instruction "POP An" pops En and then Rn. When the extension register En is popped, the least significant 6 bits are transferred to En. The register An should not be A15. The instruction "POP An, Am" pops An and then Am. The registers An and Am should not be the same LDB Rn, @[Ai+disp:4] / LDB @[Ai+disp:4], Rn The instructions transfer 8-bit data between the general register Rn and the memory location at the address of (Ai+disp:4). disp:4 is a positive displacement from 0 to 15. The general register Rn is one R0 to R7. In the instruction "LDB Rn, @[Ai+disp:4]", the 8-bit data is zero-extended to 16-bit data, and then written into Rn. In the instruction "LDB @[Ai+disp:8], Rn", the least significant byte of Rn is transferred to the memory. LDB Rn, @[Ai+disp:16] / LDB @[Ai+disp:16], Rn The instructions transfer 8-bit data between the general register Rn and the memory location at the address of (Ai+disp:16). disp:16 is a positive displacement from 0 to FFFFh. The general register Rn is one of R0 to R7. In the instruction "LDB Rn, @[Ai+disp:16]", the 8-bit data is zero-extended to 16bit data, and then written into Rn. In the instruction "LDB @[Ai+disp:16], Rn", the least significant byte of Rn is transferred to the memory. LDB R0, @[A8+disp:8] / LDB @[A8+disp:8], Rn
MCU Team LSI Division System LSI Business - 13 April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
The instructions transfer 8-bit data between the general register R0 and the memory location at the address of (A8+disp:8). disp:8 is a positive displacement from 0 to 255. In the instruction "LDB R0, @[A8+disp:8]", the 8-bit data is zero-extended to 16-bit data, and then written into R0. In the instruction "LDB @[A8+disp:8], R0", the least significant byte of R0 is transferred to the memory. LDB Rn, @[Ai+Rj] / LDB @[Ai+Rj], Rn The instructions transfer 8-bit data between the general register Rn and the memory location at the address of (Ai+Rj). The value of Rj is zero-extended to 22-bit value. The general register Rn is one of the 8 registers from R0 to R7. In the instruction "LDB Rn, @[Ai+Rj]", the 8-bit data is zero-extended to 16bit data, and then written into R0. In the instruction "LDB @[Ai+Rj], Rn", the least significant byte of Rn is transferred to the memory. LD Register, Program Memory LDC Rn, @Ai The instruction transfers 16-bit data to Rn from program memory at the address of Ai. LD Register, # immediate LD Rn, #imm:8 / LD Rn, #imm:16 / LD An, #imm:22 The instructions move an immediate data to a register. In the instruction "LD Rn, #imm:8", the immediate value is zero-extended to 16-bit value.
2.3. Branch instructions
CalmRISC16 has 2 classes of branch instructions: with a delay slot and without a delay slot. If a delay slot is filled with a useful instruction (or an instruction which is not NOP), then the performance degradation due to the control dependency can be minimized. However, if the delay slot cannot be used, then it should be NOP instruction, which can increase the program code size. In this case, the corresponding branch instruction without a delay slot can be used to avoid using NOP. Some instructions are not permitted to be in the delay slot. The prohibited instructions are as follows. All 2-word instructions All branch and jump instructions including SWI, RETD, RET_SWI, RET_IRQ, RET BREAK instructions
When a prohibited instruction is in the delay slot, the operation of CalmRISC16 is undefined or unpredictable.
BSRD eoffset:13
MCU Team LSI Division System LSI Business - 14 April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
In the instruction, called branch subroutine with a delay slot, the value (PC + 4) is saved into A14 register, the instruction in the delay slot is executed, and then the program sequence is moved to (PC + 2 + eoffset:13), where PC is the address of the instruction "BSRD eoffset:13". The immediate value eoffset:13 is sign-extended to 22-bit and then added to (PC+2). In general, the 13-bit offset field appears as a label in assembly programs. If the instruction in the delay slot reads the value of A14, the value (PC+4) is read. The even offset eoffset:13 is encoded to 12bit signed offset in instruction map by dropping the least significant bit. BRA/BRAD/BRT/BRTD/BRF/BRFD eoffset:11 In the branch instructions, the target address is (PC + 2 + eoffset:11). The immediate value eoffset:11 is sign-extended to 22-bit and then added to (PC+2). The "D" in the mnemonic stands for a delay slot. In general, the 11-bit offset field appears as a label in assembly programs. BRA and BRAD instructions always branch to the target address. BRT and BRTD instructions branch to the target address if T flag is set. BRF and BRFD instructions branch to the target address if T flag is cleared. BRAD/BRTD/BRFD instructions are delay slot branch instructions, therefore the instruction in the delay slot is executed before the branch to the target address or the branch decision is made. The even offset eoffset:11 is encoded to 10-bit signed offset in instruction map by dropping the least significant bit. BRA/BRAD EC:2, eoffset:8 In the branch instructions, the target address is (PC + 2 + eoffset:8). The immediate value eoffset:8 is sign-extended to 22-bit and then added to (PC+2). The EC:2 field indicates one of the 4 external conditions from EC0 to EC3 (input pin signals to CalmRISC16). When the external condition corresponding to EC:2 is set, the program branches to the target address. BRAD has a delay slot. The even offset eoffset:8 is encoded to 7-bit signed offset in instruction map by dropping the least significant bit. BNZD R6/R7, eoffset:8 In the branch instruction, the target address is (PC + 2 + eoffset:8). The immediate value eoffset:8 is signextended to 22-bit and then added to (PC+2). "BNZD R6, eoffset:8" instruction branches to the target address if Z0 flag is cleared. "BNZD R7, eoffset:8" instruction branches if Z1 flag is cleared. Before the branch operation, the instruction decrements R6/R7, updates Z0/Z1 flag according to the decrement result, and then executes the instruction in the delay slot. The instruction is used to manage loop counter with just one cycle overhead. In the end of the loop, the value of R6/R7 is -1. When the instruction in the delay slot read the Z0/Z1 flag, the result after the decrement is read. The even offset eoffset:8 is encoded to 7-bit signed offset in instruction map by dropping the least significant bit. JMP/JPT/JPF/JSR addr:22
MCU Team LSI Division System LSI Business - 15 April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
The target address of the instructions is addr:22. JMP always branches to the target address. JPT branches to the target address if the T flag is set. JPF branches if the T flag is cleared. JSR always branches to the target address with saving the return address (PC+4) into A14. The instructions are 2 word instructions. JMP/JPT/JPF/JSR Ai The target address of the instructions is the value of Ai. JMP always branches to the target address. JPT branches to the target address if the T flag is set. JPF branches if the T flag is cleared. JSR always branches to the target address with saving the return address (PC+2) into A14. SWI #imm:6/ RET_SWI/RET_IRQ/RET_FIQ refer to the section for interrupts. RETD The instruction branches to the address in A14 after the execution of the instruction in the delay slot. When there is no useful instruction adequate to the delay slot, "JMP A14" can be used instead of "RETD".
2.4. Bit Operation
The bit operations manipulate a bit in SR register or in a memory location. BITR/BITS/BITC/BITT @[A8+R1], #imm:3 The source as well as the destination is the 8-bit data in the data memory at the address (A8 + R1). The #imm:3 field chooses a bit position among the 8 bits. BITR resets the bit #imm:3 of the source, and then writes the result to the destination, the same memory location. BITS sets the bit #imm:3 of the source, and then writes the result to the destination. BITC complements the bit #imm:3 of the source, and then writes the result to the destination. BITT does not write any data to the destination. T flag indicates whether the bit #imm:3 of the source is zero. In other words, when the bit #imm:3 of the source is zero, T flag is set. BITR and BITS can be used to implement a semaphore mechanism or lock acquisition/release. CLRSR/SETSR/TSTSR bit bit : FE, IE, TE, Z0, Z1, V, PM CLRSR instruction clears the corresponding bit of SR. SETSR instruction sets the corresponding bit of SR. TSTSR tests whether the corresponding bit is zero, and stores the result in T flag. For example, when IE flag is zero, "TSTSR IE" instruction sets the T flag. We can clear the T flag by the instruction "CMP GT, R0, R0". We can set the T flag by the instruction "CMP EQ, R0, R0".
MCU Team LSI Division System LSI Business
- 16 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
2.5. Miscellaneous instructions
SYS #imm:5 The instruction activates the output port nSYSID. The #imm:5 is transferred to outside on DA[4:0]. The most significant 17 bits remain unchanged. The instruction is for system command to outside such as power down modes. COP #imm:13 The instruction activates the output port nCOPID. The #imm:13 is transferred to outside on COPIR[12:0]. The instruction is used to transfer instruction to coprocessor. The #imm:13 may be from 200h to 1FFFh. CLD Rn, #imm:5 / CLD #imm:5, Rn The instruction activates the output port nCOPID, nCLDID, and CLDWR. The least significant 13 bits of the instruction is transferred to outside on COPIR[12:0]. The #imm:5 is transferred to outside on DA[4:0]. The instructions move 16-bit data between Rn and a coprocessor register implied by the #imm:5 field. CLDWR signal indicates whether the data movement is from CalmRISC16 to coprocessor. The register Rn is one 8 registers from R0 to R7. NOP No operation. BREAK The software break instruction activates nBRK signal, and holds PA for one cycle. It's for debugging operation.
3. CalmRISC16 Instruction Map
15 ADD Rn, #imm:7 SUB Rn, #imm:7 LD Rn, #imm:8 LDW LDW LDW LDW LDW Rn, @[SP + edisp:9] @[SP + edisp:9], Ri Rn, @[Ai + edisp:5] Rn, @[Ai + Rj] @[An + edisp:5], Ri 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 1 0 0 0 0 0 1 0 1 0 0 1 Rn Rn Rn Rn Ri Rn Rn Ri 0 1 0 Ai Ai An 8 7 0 1 Imm:7 Imm:7 Imm:8 Edisp:9 Edisp:9 Edisp:5 Rj Edisp:5 0
MCU Team LSI Division System LSI Business
- 17 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 0 0 1 1 Ri Dn Dn An An Di Di Ai Ai Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn 0 0 1 1 0 0 1 1 1 1 0 0 0 1 0 1 0 1 0 0 1 1 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 An Ai Ai Ai Ai An An An An 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 Rm Disp:4 Rj Disp:4 Rj Disp:4 Rm Disp:4 Rm Ri Ri Ri Ri Ri Ri Ri Ri Ri Ri Ri Ri Ri Ri Rn Rn Rn Rn Rn Rn Ai Ai Ai Ai Rn Rn
April 2000
LDW
@[An + Rm], Ri
LDB Dn, @[Ai + disp:4] LDB Dn, @[Ai + Rj] LDW An, @[Ai + disp:4] LDW An, @[Ai + Rj] LDB @[An + disp:4], Di LDB @[An + Rm], Di LDW @[An + disp:4], Ai LDW @[An + Rm], Ai ADD Rn, Ri SUB ADC SBC Rn, Ri Rn, Ri Rn, Ri
AND Rn, Ri OR XOR TST CMP CMP CMPU CMPU CMP LD Rn, Ri Rn, Ri Rn, Ri GE, Rn, Ri GT, Rn, Ri GE, Rn, Ri GT, Rn, Ri EQ, Rn, Ri Rn, Ri
RR Rn RL Rn
RRC Rn SRB Rn SR Rn SRA Rn JPF Ai JPT Ai
JMP Ai JSR Ai SLB Rn DT Rn
MCU Team LSI Division System LSI Business
- 18 -
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 Dn 0 0 1 1 0 0 1 1 1 1 1 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Imm:8 Imm:8 Imm:8 Imm:8 Imm:8 Disp:8 Disp:8 0 0 1 1 0 1 0 1 Bs:3 Bs:3 Bs:3 Bs:3 Imm:5 Imm:6
April 2000
INCC Rn DECC Rn COM Rn COM2 Rn
Rn Rn Rn Rn Rn Rn Rn 0 1 An An Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn
COMC Rn EXT Rn
ADD Rn, #imm:16 ADD An, #imm:16 SUB An, #imm:16 ADC Rn, #imm:16 SBC Rn, #imm:16 AND Rn, #imm:16 OR Rn, #imm:16 XOR Rn, #imm:16 TST Rn, #imm:16
CMP GE, Rn, #imm:16 CMP GT, Rn, #imm:16 CMPU GE, Rn, #imm:16 CMPU GT, Rn, #imm:16 CMP EQ, Rn, #imm:16 LD Rn, #imm:16 Reserved CMP EQ, Dn, #imm:8 AND R0, #imm:8 OR R0, #imm:8 XOR R0, #imm:8 TST R0, #imm:8
LDB R0, @[A8+ disp:8] LDB @[A8+ disp:8],R0 BITR @[A8+R1], bs:3 BITS @[A8+R1], bs:3 BITC @[A8+R1], bs:3 BITT @[A8+R1], bs:3
SYS #imm:5 SWI #imm:6
MCU Team LSI Division System LSI Business
- 19 -
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 1
April 2000
CLRSR bs:3 SETSR bs:3 TSTSR bs:3 NOP BREAK LD R0, SR LD SR, R0 RET_FIQ RET_IRQ RET_SWI RETD LD R0, SPCL_FIQ LD R0, SPCH_FIQ LD R0, SSR_FIQ Reserved LD R0, SPCL_IRQ LD R0, SPCH_IRQ LD R0, SSR_IRQ Reserved Reserved LD R0, SSR_SWI Reserved Reserved LD SPCL_FIQ, R0 LD SPCH_FIQ, R0 LD SSR_FIQ, R0 Reserved LD SPCL_IRQ, R0 LD SPCH_IRQ, R0 LD SSR_IRQ, R0 Reserved Reserved LD SSR_SWI, R0 Reserved Reserved
Bs:3 Bs:3 Bs:3 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0 0 1 1 0 0 1 1 0 1 1
0 1 0 1 0 1 0 1
0 1
MCU Team LSI Division System LSI Business
- 20 -
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 21 -
Reserved Reserved LD An, PC Reserved JPF adr:22 JPT adr:22
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 Rn
1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1
1 1 1 1 0 0 1 1 0 0
1 1 1 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1
0 1 1 1 0 1 1 0 1 Adr[21:16] Adr[21:16] Adr[21:16] Adr[21:16] 0 0 0 0 0 0 1 1 1 1 1 1 0 0 1 1 1 1 0 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 Imm:6 0 1 imm:5 imm:5 Imm[21:16] Imm[21:16] 0 0 0 0 0 0 1 1 1 1 0 0 1 1 1 1 0 0 0 1 0 1 0 1 0 1 1 0 An Rn
April 2000
An
JMP adr:22 JSR adr:22 LDC Rn, @Ai Reserved LD Dn, Ei LD En, Di CMP EQ, An, Ai LD An, Ai LDW LDW Rn, @[Ai+disp:16] @[An+disp:16], Ri
Ai
0 0 1 1
Dn Di An An Rn Ri
0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
Ei En Ai Ai Ai An Ai An Ai An
LDB Dn, @[Ai+disp:16] LDB @[An+disp:16], Di LDW An, @[Ai+disp:16] LDW @[An+disp:16], Ai CMP GE, Dn, #imm:6 ADD An, #imm:5 SUB An, #imm:5 CMP EQ, An, #imm:22 LD An, #imm:22 ADD An, Ri SUB An, Ri MUL MUL MUL MUL UU, Dn, Di US, Dn, Di SU, Dn, Di SS, Dn, Di
0 0 1 1 0 1 1 0 1 0 1 0 0 1 1
Dn Di An Ai Dn An An An An An An Dn Dn Dn Dn Rm
Ri Ri Di Di Di Di Rn
POP Rn[, Rm] Reserved POP An[, Am] PUSH Rn[, Rm]
0 1 Am Rm
1 1
MCU Team LSI Division System LSI Business
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 0 1 0 1 0 1 0 0 0 0 0 1 0 1 1 EC:2 H 0 1 Eoffset:11 Eoffset:11 Eoffset:11 Eoffset:11 Eoffset:11 Eoffset:11 imm:5 imm:5 Imm:13 0 1 Dn Di Eoffset:8 Eoffset:8 EC:2 0 1 Am 1 1 1 1 1 1 1 1 1 1 An
Reserved PUSH BSRD An[, Am] eoffset:13
Eoffset:13 Eoffset:8
BRA EC:2, eoffset:8 Reserved BRAD EC:2, eoffset:8 BNZD H, eoffset:8 Reserved BRA eoffset:11 BRAD eoffset:11 BRF eoffset:11 BRFD eoffset:11 BRT eoffset:11
BRTD eoffset:11 CLD Dn, imm:5 CLD imm:5, Di COP imm:13
Dn[15:0] An[21:0] En[5:0] EC:2 Eoffset
: R0 ~ R7 : A8 ~ A15, concatenation of En and Rn : E8 ~ E15, MS 6-bit of An : EC0,EC1,EC2,EC3 : even signed offset
H[15:0] : R6, R7 SP Disp Edisp : equal to A15 : unsigned displacement : even unsigned displacement
4. Quick Reference
Instruction ADD SUB op1 Rn op2 #imm:7 Ri #imm:8 LD Rn #imm:16 Ri op1 <- op2 Z0, Z1 operation op1 <- op1 + op2 op1 <- op1 + ~op2 + 1 flag T=C, Z0, Z1,V
MCU Team LSI Division System LSI Business
- 22 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
@[SP+edisp:9]
LDW
Rn
@[Ai+edisp:5] @[Ai+Rj] @[Ai+disp:16]
op1 <- op2
-
@[SP+edisp:9] LDW @[An+edisp:5] @[An+Rm] @[Ai+disp:16] @[Ai+edisp:5] LDW An @[Ai+Rj] @[Ai+disp:16] @[An+edisp:5] LDW @[An+Rm] @[Ai+disp:16] @[SP+disp:8] LDB Dn @[Ai+disp:4] @[Ai+Rj] @[Ai+disp:16] LDB R0 @[SP+disp:8] LDB @[An+disp:4] @[Ai+Rj] @[Ai+disp:16] LDB ADC SBC AND OR XOR TST CMP GE CMP GT CMPU GE CMPU GT CMP EQ
MCU Team LSI Division System LSI Business - 23 -
Ri
op1 <- op2
-
op1 <- op2
-
Ai
op1 <- op2
-
op1<-{8'h0,op2[7:0]}
-
@[A8+disp:8]
op1<-{8'h0,op2[7:0]}
-
Di
op1 <- op2[7:0]
-
@[A8+disp:8] Rn
R0 Ri #imm:16 Ri #imm:16 Ri #imm:16
op1 <- op2[7:0] op1 <- op1 + op2 + T op1 <- op1 + ~op2 + T op1 <- op1 & op2 op1 <- op1 | op2 op1 <- op1 ^ op2 op1 & op2 op1 + ~op2 + 1, T=~N
T=C,V, Z0,Z1 T=Z, Z0,Z1
Rn
Rn
T=Z
Rn
Ri #imm:16
op1 + ~op2 + 1, T=~N&~Z op1 + ~op2 + 1, T=C op1 + ~op2 + 1, T=C&~Z op1 + ~op2 + 1, T=Z
April 2000
T
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
op1 <- {op1[0],op1[15:1]} op1 <- {op1[14:0],op1[15]} op1 <- {T,op1[15:1]} T=op1[0] T=op1[15] T=op1[0] T=op1[7] T=op1[0] T=op1[0] T= op1[8] T=Z, Z0,Z1,V T=Z,Z0, Z1
RR RL RRC SRB SR SRA SLB DT Rn Rn -
op1 <- {8'h00,op1[15:8]} op1 <- {0,op1[15:1]} op1 <- {op1[15],op1[15:1]} op1 <- {op1[7:0],8'h00} op1 <- op1 + 0xffff
COM INCC DECC COM2 COMC EXT JPF JPT JMP JSR ADD
Rn
Op1 <- ~op1 op1 <- op1 + T
Rn
op1 <- op1 + 0xffff + T op1 <- ~op1 + 1 op1 <- ~op1 + T
T=C,Z0, Z1
Rn
op1<-{8{op1[7]},op1[7:0]} if(T==0) PC <- op1
Z0, Z1
Ai addr:22
if(T==1) PC <- op1 PC <- op1 A14 <- PC+(2|4), PC<-op1
-
Rn
#imm:16 #imm:16
op1 <- op1 + op2
T=C, Z0,Z1,V
ADD SUB CMP EQ AND OR XOR TST BITR BITS BITC BITT SYS SWI
An
#imm:5 Ri
op1 <- op1 + op2 op1 <- op1 - op2 op1 + ~op2 + 1 Op1 <- op1 & {8'h00,op2}
-
Dn
#imm:8
T=Z
R0
#imm:8
op1 <- op1 | {8'h00,op2} op1 <- op1 ^ {8'h00,op2} op1 & {8'h00,op2} op1[op2] <- 0
T=Z8
@[A8+R1]
bs:3
op1[op2] <- 1 op1[op2] <- ~op1[op2] op1[op2] <- op1[op2]
T= op1[op2]
#imm:5 #imm:6
MCU Team LSI Division System LSI Business
DA[4:0] <- op1 A14 <- PC+2, PC <- op2*4
- 24 -
IE, TE
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
SR[op1] <- 0
CLRSR SETSR TSTSR RETD SR SPCL_FIQ SPCH_FIQ LD R0 SSR_FIQ SPCL_IRQ SPCH_IRQ SSR_IRQ SSR_SWI SR SPCL_FIQ SPCH_FIQ LD SSR_FIQ SPCL_IRQ SPCH_IRQ SSR_IRQ SSR_SWI PC LD An Ai #imm:22 CMP EQ LDC LD LD CMP GE MUL UU MUL US MUL SU MUL SS Dn Di An Rn Rn En Dn Ai #imm:22 @Ai Ei Ri #imm:6 R0 bs:3 -
SR[op1] <- 1 T <- ~SR[op1] PC <- A14
-
-
op1 <- op2
-
op1 <- op2
op1 <- op2 + 4 op1 <- op2 op1 <- op2 op1 + ~op2 + 1 op1 <- PM[op2] op1 <- {10'h000, op2} op1 <- op2[5:0] op1 + ~op2 + 1 op1<-{0,op1[7:0]} * {0,op2[7:0]} op1<-{0,op1[7:0]}*{op2[7],op2[7:0]} op1<-{op1[7],op1[7:0]}*{0,op2[7:0]} op1 <-{op1[7],op1[7:0]}* {op2[7],op2[7:0]} T=Z22 T=~N -
POP
Rn
Rm
op1<-@[SP+2], op2<-@[SP+4], SP<-SP+4
- 25 -
-
MCU Team LSI Division System LSI Business
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
Rm Am @[SP]<-op1,@[SP-2]<-op2,SP<-SP-4 En<-@[SP+2], Rn<-@[SP+4], Em<@[SP+6], Rm<-@[SP+8], SP<-SP+8 @[SP]<-Rn, @[SP-2]<-En, @[SP-4]PUSH POP
Rn An
PUSH BSRD BRA/BRAD BNZD
An eoffset:13 EC:2 R6
Am eoffset:8 eoffset:8
Z0
BNZD BRA/BRAD BRF/BRFD BRT/BRTD CLD CLD COP
R7 eoffset:11 eoffset:11 eoffset:11 Dn imm:5 imm:13
eoffset:8 imm:5 Di -
Z1 -
MCU Team LSI Division System LSI Business
- 26 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
ADC (1)
Add with Carry Register
ADC Rn, Ri
Description
The ADC (Add with Carry Register) instruction is used to synthesize 32-bit addition. If register pairs R0, R1 and R2, R3 hold 32-bit values (R0 and R2 hold the least-significant word), the following instructions leave the 32-bit sum in R0, R1: ADD R0, R2 ADC R1, R3 The instruction ADC R0, R0 produces a single-bit Rotate Left with Carry (17-bit rotate through the carry) on R0. ADC adds the value of register Rn, and the value of the Carry flag (stored in the T bit), and the value of register Ri, and stores the result in register Rn. The T bit and the V flag are updated based on the result.
15
14
13
12
11
8
7
6
5
4
3
0
1
0
0
0
Rn
0
0
1
0
Ri
Operation
Rn := Rn + Ri + T bit T bit := Carry from (Rn + Ri + T bit) V flag := Overflow from (Rn + Ri + T bit) if(Rn == R6/R7) Z0/Z1 flag := ((Rn + Ri + T) == 0)
Exceptions Notes
None. None.
MCU Team LSI Division System LSI Business
- 27 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
ADC (2)
Add with Carry Immediate
ADC Rn, #
Description
The ADC (Add with Carry Immediate) instruction is used to synthesize 32-bit addition with an immediate operand. If register pair R0, R1 holds a 32-bit value (R0 holds the least-significant word), the following instructions leave the 32-bit sum with 87653456h in R0, R1: ADD R0, #3456h ADC R1, #8765h ADC adds the value of register Rn, and the value of the Carry flag (stored in the T bit), and the 16-bit immediate operand, and stores the result in register Rd. The T bit and the V flag are updated based on the result.
15
14
13
12
11
10
9
8
7
6
5
4
3
0
1
0
0
0
0
0
1
0
1
1
1
1
Rn
Operation
Rn := Rn + + T bit T bit := Carry from (Rn + + T bit) V flag := Overflow from (Rn + + T bit) if(Rn == R6/R7) Z0/Z1 flag := ((Rn + ) == 0)
Exceptions Notes
None. This is a 2-word instruction, where the 16-bit immediate follows the instruction word shown above. Unlike 1-word instructions, therefore, fetching of ADC Rn, takes 2 cycles.
MCU Team LSI Division System LSI Business
- 28 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
ADD (1)
Add Register
ADD Rn, Ri
Description
The ADD (Add Register) instruction is used to add two 16-bit values in registers. 32-bit addition can be achieved by executing ADC instruction in pair with this instruction (see page 27). ADD adds the value of register Rn, and the value of register Ri, and stores the result in register Rn. The T bit and the V flag are updated based on the result.
15
14
13
12
11
8
7
6
5
4
3
0
1
0
0
0 Rn := Rn + Ri
Rn
0
0
0
0
Ri
Operation
T bit := Carry from (Rn + Ri) V flag := Overflow from (Rn + Ri) if(Rn == R6/R7) Z0/Z1 flag := ((Rn + Ri) == 0)
Exceptions Notes
None. None.
MCU Team LSI Division System LSI Business
- 29 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
ADD (2)
Add Small Immediate
ADD Rn, #
Description
This form of ADD instruction is used to add a 7-bit (positive) immediate value to a register ADD adds the value of register Rn, and the value of , and stores the result in register Rn. The T bit and the V flag are updated based on the result.
15
14
13
12
11
8
7
6
0
0
0
0
0
Rn
0

Operation
Rn := Rn + T bit := Carry from (Rn + ) V flag := Overflow from (Rn + ) if(Rn == R6/R7) Z0/Z1 flag := ((Rn + ) == 0)
Exceptions Notes
None. is an unsigned amount.
MCU Team LSI Division System LSI Business
- 30 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
ADD (3)
Add Immediate
ADD Rn, #
Description
The ADD (Add Immediate) instruction is used to add a 16-bit immediate value to a register. 32-bit addition or subtraction can be achieved by executing ADC or SBC instruction in pair with this instruction (see page 28 and 99 for examples). ADD adds the value of register Rn, and the value of , and stores the result in register Rn. The T bit and the V flag are updated based on the result.
15
14
13
12
11
10
9
8
7
6
5
4
3
0
1
0
0
0
0
0
0
0
1
1
1
1
Rn
Operation
Rn := Rn + T bit := Carry from (Rn + ) V flag := Overflow from (Rn + ) if(Rn == R6/R7) Z0/Z1 flag := ((Rn + ) == 0)
Exceptions Notes
None. This is a 2-word instruction, where the 16-bit immediate follows the instruction word shown above. Unlike 1-word instructions, therefore, fetching of ADD Rn, takes 2 cycles. The instruction "SUB Rn, #" does not exist. The result of "SUB Rn, #" instruction is identical with the result of "ADD Rn, #(2's complement of )" except when is zero. In that case, "SUB Rn, #" can be used.
MCU Team LSI Division System LSI Business
- 31 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
ADD (4)
Add Extended Register
ADD An, Ri
Description
The ADD (Add Extended Register) instruction is used to add a 16-bit unsigned register value to a 22-bit register. This instruction adds the value of 16-bit register Ri, and the value of 22-bit register An, and stores the result in register An.
15
14
13
12
11
10
8
7
6
5
4
3
0
1
0
1
0
0
An
1
1
0
0
Ri
Operation Exceptions Notes
An := An + Ri None. None.
MCU Team LSI Division System LSI Business
- 32 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
ADD (5)
Add Immediate to Extended Register
ADD An, #
Description
This form of ADD instruction is used to add a 16-bit unsigned immediate value to a 22-bit register. This instruction adds the value of to the value of An, and stores the result in register An
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
1
0
0
0
0
0
0
1
1
1
1
1
0
An
Operation Exceptions Notes
An := An + None. This is a 2-word instruction, where the 16-bit immediate follows the instruction word shown above. Unlike 1-word instructions, therefore, fetching of this instruction takes 2 cycles.
MCU Team LSI Division System LSI Business
- 33 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
ADD (6)
Add 5-bit Immediate to Extended Register
ADD An, #
Description
This form of ADD instruction is used to add a 5-bit unsigned immediate value to a 22-bit register. This instruction adds the value of 5-bit immediate , and the value of 22bit register An, and stores the result in register An.
15
14
13
12
11
10
8
7
6
5
4
0
1
0
1
0
1
An
0
1
0

Operation Exceptions Notes
An := An + None. is an unsigned amount.
MCU Team LSI Division System LSI Business
- 34 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
AND (1)
AND Register
AND Rn, Ri
Description
The AND (AND Register) instruction is used to perform bitwise AND operation on two values in registers, Rn and Ri. The result is stored in register Rn. The T bit is updated based on the result.
15
14
13
12
11
8
7
6
5
4
3
0
1
0
0
0 Rn := Rn & Ri
Rn
0
1
0
0
Ri
Operation
T bit := ((Rn & Ri) == 0) if(Rn == R6/R7) Z0/Z1 flag := ((Rn & Ri) == 0)
Exceptions Notes
None. None.
MCU Team LSI Division System LSI Business
- 35 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
AND (2)
AND Small Immediate
AND R0, #
Description
The AND (AND Small Immediate) instruction is used to perform an 8-bit bitwise AND operation on two values in register R0 and . The result is stored in register R0. The T bit is updated based on the result.
15
14
13
12
11
10
9
8
7
0
1
0
0
1
1
0
0
0

Operation Exceptions Notes
R0 := R0 & T bit := ((R0 & )[7:0] == 0) None. The register used in this operation is fixed to R0. Therefore, the operand should be placed in R0 before this instruction executes. is zero-extended to a 16-bit value before operation.
MCU Team LSI Division System LSI Business
- 36 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
AND (3)
AND Large Immediate
AND Rn, #
Description
This type of AND instruction is used to perform bitwise AND operation on two values in register Rn and . The result is stored in register Rn. The T bit is updated based on the result.
15
14
13
12
11
10
9
8
7
6
5
4
3
0
1
0
0
0
0
1
0
0
1
1
1
1
Rn
Operation
Rn := Rn & T bit := ((Rn & ) == 0) if(Rn == R6/R7) Z0/Z1 flag := ((Rn & ) == 0)
Exceptions Notes
None. This is a 2-word instruction, where the 16-bit immediate follows the instruction word shown above. Unlike 1-word instructions, therefore, fetching of this instruction takes 2 cycles.
MCU Team LSI Division System LSI Business
- 37 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
BITop
BIT Operation
BITop @[A8+R1], #
Description
The BITop (Bit Operation) instruction is used to perform a bit operation on an 8-bit memory value. The allowed operations include reset (BITR), set (BITS), complement (BITC), and test (BITT). BITop fetches the value of memory location specified by @(A8+R1), performs the specified operation on the specified bit, and stores the result back into the same memory location
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
1
0
0
1
1
1
1
0
0
0
0
OP

Operation
Temp := MEM[A8+R1] T bit := ~Temp[] if (BITop != BITT) { Result := BITop(Temp, ) MEM[A8+R1] := Result } Here, BITop is BITR (OP == 00) | BITS (01) | BITC (10) | BITT (11). The bit location of these operations is specified by .
Exceptions Notes
None. The address used to access data memory is obtained from the addition of two registers A8 and R1. No other registers can be used for this address calculation.
MCU Team LSI Division System LSI Business
- 38 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
BNZD
Branch Not Zero with Autodecrement
BNZD H,
Description
The BNZD (Branch Not Zero with Delay Slot) instruction is used to change the program flow when the specified register value does not evaluate to zero. After evaluation, the value in register is automatically decremented. A typical usage of this instruction is as a backward branch at the end of a loop. LOOP: ... BNZD R6, LOOP ADD R4, 3 // if (Z0 != 0) go back to LOOP // delay slot
In the above example, R6 is used as the loop counter. After specified loop iterations, BNZD is not taken and the control will come out of the loop, and R6 will have -1. For a loop with "N" iterations, the counter register used should be initially set to is taken or not.
15 14 13 12 11 10 9 8 7 6 0
"(N-1)". BNZD has a single delay slot; the instruction that
immediately follows BNZD will be executed always regardless of whether BNZD
1
1
0
0
0
1
1
H
0

Operation
if(H == R6) { if(Z0 != 0) PC := PC + 2 + R6 := R6 - 1 Z0 := ((R6-1) == 0) } else { } H is a register specifier denoting either R6 or R7. // H == R7 Same mechanism as the case R6
Exceptions Notes
None. When BNZD checks if H is zero by looking up the Z0 (for R6) or Z1 (for R7) bit in SR, these flags are updated as BNZD decrements the value of the register. For the first iteration, however, the user is responsible for resetting the flag, Z0 or Z1, before the loop starts execution.
MCU Team LSI Division System LSI Business
- 39 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
BR
Conditional Branch
BRtype
Description
The BR (Conditional Branch) instruction is used to change the program flow conditionally or unconditionally. The allowed forms of the instruction include BRA (always), BRAD (always with delay slot), BRT (when T bit is set), BRTD (when T bit is set, with delay slot), BRF (when T bit is clear), and BRFD (when T bit is clear, with delay slot). The branch target address is calculated by 1. sign-extending to 22 bits 2. adding this to the PC (which contains the address of the branch instruction plus 1)
15
14
13
12
11
10
9
0
1
1
0
if (Condition)
D

Operation
PC := PC + 2 + Here, the field determines whether this branch is BRA (01), BRF (10), or BRT (11). If D is set, the branch instruction has one branch delay slot, meaning that the instruction following the branch will be executed always, regardless of the branch outcome. If D is clear, the immediately following instruction is NOT executed if the branch is taken.
Exceptions Notes
None. None.
MCU Team LSI Division System LSI Business
- 40 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
BRA EC
Branch on External Condition
BRA(D) EC:2
Description
The BRA EC (Branch on External Condition) instruction is used to change the program flow when a certain external condition is set. A typical usage of this instruction is to branch after a coprocessor operation as shown below: COP NOP NOP BRA EC0 OVERFLOW ... OVERFLOW: ... ... The BRA EC instruction checks the specified external condition (instead of checking the T bit as other branch instructions, see page 40) and branch to the specified program address. There can be up to 4 external conditions, specified by the field in the instruction.
15
14
13
12
11
10
9
8
7
6
0
1
1
0
0
0
D
0


Operation
if (ExternalCondition_n == True) PC := PC + 2 +
Exceptions Notes
None. None.
MCU Team LSI Division System LSI Business
- 41 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
BREAK
BREAK
BREAK
Description
The BREAK instruction suspends the CalmRISC core for 1 cycle by keeping PC from increasing. Processor resumes execution after 1 cycle. This instruction is used for debugging purposes only and thus should not be used in normal operating modes. A core signal nBRK is asserted low for the cycle.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
0
1
1
1
1
0
1
0
0
1
1
0
0
1
Operation Exceptions Notes
No operation with PC suspended for a single cycle. None. None.
MCU Team LSI Division System LSI Business
- 42 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
BSRD
Branch Subroutine with Delay Slot
BSRD
Description
The BSRD (Branch Subroutine with Delay slot) instruction is used to change the program flow to a subroutine by assigning the address of the subroutine to PC after saving the return address (PC+4) in the link register, or A14. The address of the subroutine is calculated by: 1. sign-extending to 22 bits 2. adding this to the PC (which contains the address of the branch instruction plus 1) After executing the subroutine, the program flow can return back to the instruction that follows the BSRD instruction by setting PC with the value stored in A14 (see JMP Ai instruction in page 58 and RET instruction in page 91). This instruction has a delay slot; the instruction that immediately follows BSRD will be always executed.
15
14
13
12
11
0
1
0
1
1 A14 := PC + 4 PC := PC + 2 +

Operation Exceptions Notes
None. None.
MCU Team LSI Division System LSI Business
- 43 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
CLD
Coprocessor Load
CLD Dn, / CLD , Di
Description
The CLD (Coprocessor Load) instruction is used to transfer data from and to coprocessor by generating the core signals nCLDID and CLDWR. The content of DA[4:0] is , the address of coprocessor register to be read or written. When a data item is read from coprocessor (CLD Dn, ), it is stored in Dn. When a data item is written to coprocessor, it should be prepared in Di.
15
14
13
12
11
10
8
7
6
5
4
0
1
1
1
0
0
0
0
imm:5
M
Dn/Di
Operation
(M == 0, read) DA[4:0] := nCLDID := 0 CLDWR := 0 Dn := () (M == 1, write) DA[4:0] := nCLDID := 0 CLDWR := 1 () := Di
Exceptions Notes
None. None.
MCU Team LSI Division System LSI Business
- 44 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
CLRSR
Clear SR
CLRSR bs:3
Description
The CLRSR (Clear SR) instruction is used to clear a specified bit in SR as follows: CLRSR FE / IE / TE / V / Z0 / Z1 / PM To clear the T bit, one can do as follows: CMP GT, R0, R0 To turn on a specified bit in SR, the SETSR instruction (in page 100 ) is used.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
1
0
0
1
1
1
1
0
1
0
0
0
0

Operation Exceptions Notes
SR[] := 0 None. None.
MCU Team LSI Division System LSI Business
- 45 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
CMP (1)
Compare Register
CMPmode Rn, Ri
Description
The CMP (Compare Register) instruction is used to compare two values in registers Rn and Ri. The allowed modes include GE (Greater or Equal), GT (Greater Than), UGE (Unsigned Greater or Equal), UGT (Unsigned Greater Than), and EQ (Equal). CMP subtracts the value of Ri from the value of Rn and performs comparison based on the result. The contents of Rn and Ri are not changed after this operation. The T bit is updated for later reference.
15
14
13
12
11
8
7
6
5
4
3
0
1
0
0
0 Temp := Rn - Ri
Rn
1

Ri
Operation
T bit := ~Negative ~Negative && ~Zero Carry Carry && ~Zero Zero
if ( == GE) if ( == GT) if ( == UGE) if ( == UGT) if ( == EQ)
encoding: GE (000), GT (001), UGE (010), UGT (011), and EQ (100).
Exceptions Notes
None. None.
MCU Team LSI Division System LSI Business
- 46 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
CMP (2)
Compare Immediate
CMPmode Rn, #
Description
The CMP (Compare Immediate) instruction is used to compare two values in register Rn and . The allowed modes include GE (Greater or Equal), GT (Greater Than), UGE (Unsigned Greater or Equal), UGT (Unsigned Greater Than), and EQ (Equal). CMP subtracts the value of from the value of Rn and performs comparison based on the result. The contents of Rn is not changed, however, after this operation. The T bit is updated for later reference.
15
14
13
12
11
10
8
7
6
5
4
3
0
1
0
0
0
1

1
1
1
1
Rn
Operation
Temp := Rn - T bit := ~Negative ~Negative && ~Zero Carry Carry && ~Zero Zero if ( == GE) if ( == GT) if ( == UGE) if ( == UGT) if ( == EQ)
encoding: GE (000), GT (001), UGE (010), UGT (011), and EQ (100).
Exceptions Notes
None. This is a 2-word instruction, where the 16-bit immediate follows the instruction word shown above. Unlike 1-word instructions, therefore, fetching of CMPmode # takes 2 cycles.
MCU Team LSI Division System LSI Business
- 47 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
CMP (3)
Compare Short Immediate
CMP GE, Dn, #
Description
The CMP (Compare Immediate) instruction is used to perform signed-comparison of the register Dn and an unsigned immediate value . Dn is one of the registers from R0 to R7. CMP subtracts the value of from the value of Dn and performs signed-comparison based on the result. The contents of Dn is not changed, however, after this operation. The T bit is updated for later reference.
15
14
13
12
11
10
8
7
6
5
4
3
0
1
0
1
0
0
Dn
0
1
imm:6
Operation Exceptions Notes
T bit := ~Negative of (Rn - )
None. None
MCU Team LSI Division System LSI Business
- 48 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
CMPEQ (1)
Compare Equal Extended Register
CMP EQ, An, Ai
Description
The CMP EQ (Compare Equal Extended Register) instruction is used to compare two values in registers An and Ai. This instruction is a restricted form of more general CMPmode instructions for a 22-bit equality comparison between register values.
15
14
13
12
11
10
8
7
6
5
4
3
2
0
1
0
1
0
1
An
0
0
0
1
0
Ai
Operation
T bit := (An == Ai) An or Ai refers to registers from A8 to A15 with their 6-bit extensions.
Exceptions Notes
None. None.
MCU Team LSI Division System LSI Business
- 49 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
CMPEQ (2)
Compare Equal Small Immediate
CMP EQ, Dn, #
Description
The CMP EQ (Compare Equal Small Immediate) instruction is used to compare two values in register Dn and . is zero-extended to 16 bits before comparison. This instruction is a restricted form of more general CMPmode instructions for an 8-bit equality comparison between a register value and an immediate value.
15
14
13
12
11
10
8
7
0
1
0
0
1
0
Dn

Operation
T bit := ((Dn - ) == 0) Dn refers to registers R0 - R8.
Exceptions Notes
None. None.
MCU Team LSI Division System LSI Business
- 50 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
CMPEQ (3)
Compare Equal Large Immediate
CMP EQ An, #
Description
The CMP EQ (Compare Equal Large Immediate) instruction is used to compare two values in register An and . This instruction is a restricted form of more general CMPmode instructions for a 22-bit equality comparison between a register value and an immediate value.
15
14
13
12
11
10
8
7
6
5
0
1
0
1
0
0
An
1
0
[21:16]
Operation
T bit := Zero from (An - ) An refers to registers from A8 to A15 with their 6-bit extensions.
Exceptions Notes
None. This is a 2-word instruction, where the 16-bit immediate ([15:0]) follows the instruction word shown above. Unlike 1-word instructions, therefore, fetching of CMP EQ takes 2 cycles.
MCU Team LSI Division System LSI Business
- 51 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
COM
Complement
COMmode Rn
Description
The COM (Complement) instruction is used to compute 1's or 2's complement of a register value Rn. Utilizing various modes, 32-bit complement operation can be done. If register pair R0, R1 holds a 32-bit value (R0 holds the least-significant word), the following instructions leave the 32-bit 2's complement in R0, R1: COM2 R0 COMC R1 // 2's complement // 2's complement with carry
COM computes the 1's complement of the value of register Rn. COM2 computes the 2's complement, and COMC computes the 2's complement value when T bit has been set. If T bit is clear, COM2 is equivalent to COM.
15
14
13
12
11
10
9
8
7
6
5
4
3
0
1
0
0
0
1
1

1
1
1
0
Rn
Operation
if ( == 00) { Rn := ~Rn T bit := (Rn == 0) } if ( == 01) { Rn := ~Rn + 1
// COM
// COM2
T bit := Carry from (~Rn + 1) } if ( == 10) { Rn := ~Rn + T bit T bit := Carry from (~Rn + T) } Encoding of : 00: COM, 01: COM2, 10: COMC if(Rn == R6/R7) Z0/Z1 := Zero flag of the result. // COMC
Exceptions Notes
None. None.
MCU Team LSI Division System LSI Business
- 52 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
COP
Coprocessor
COP
Description
The COP (Coprocessor) instruction is used to perform a coprocessor operation, specified by . Certain coprocessor operations set external conditions, upon which branches can be executed (see BRECn instructions, from page 41). The should be greater or equal to 0x200.
15
14
13
12
0
1
1
1
Perform a coprocessor operation by placing signals on core output pins as follows: Core output signal COPIR[12:0] := Core output signal nCOPID := LOW
Operation
Exceptions Notes
None. None.
MCU Team LSI Division System LSI Business
- 53 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
DECC
Decrement with Carry
DECC Rn
Description
The DECC (Decrement with Carry) instruction is used to synthesize 32-bit decrement. If register pair R0, R1 holds a 32-bit value (R0 holds the leastsignificant word), the following instructions leave the 32-bit decremented value in R0, R1: DEC R0 DECC R1 DECC decrements the value of Rn by 1 only if the Carry flag (stored in the T bit) is clear, and stores the result back in register Rn. The T bit and the V flag are updated based on the result. // this is implemented by ADD R0, -1
15
14
13
12
11
10
9
8
7
6
5
4
3
0
1
0
0
0
1
0
1
1
1
1
1
0
Rn
Operation
Rn := Rn - 1 + T bit T bit := Carry from (Rn - 1 + T bit) V flag := Overflow from (Rn -1 + T bit) if(Rn == R6/R7) Z0/Z1 := ((Rn - 1 + T) == 0)
Exceptions Notes
None. None.
MCU Team LSI Division System LSI Business
- 54 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
DT
Decrement and Test
DT Rn
Description
The DT (Decrement and Test) instruction is used to decrement the value of a specified register and test it. This instruction provides a compact way to control register indexing for loops. The T bit and the V flag are updated based on the result.
15
14
13
12
11
10
9
8
7
6
5
4
3
0
1
0
0
0
1
0
0
1
1
1
1
0
Rn
Operation
Rn := Rn - 1 T bit := ((Rn - 1) == 0) V flag := Overflow from (Rn - 1) if(Rn == R6/R7) Z0/Z1 := ((Rn - 1) == 0)
Exceptions Notes
None. None.
MCU Team LSI Division System LSI Business
- 55 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
EXT
Sign-Extend
EXT Rn
Description
The EXT (Sign Extend) instruction is used to sign-extend an 8-bit value in Rn. This instruction copies Rn[7] to Rn[15:8].
15
14
13
12
11
10
9
8
7
6
5
4
3
0
1
0
0
0
1
1
1
1
1
1
1
0
Rn
Operation Exceptions Notes
All bits from Rn[15] to Rn[8] := Rn[7] if(Rn == R6/R7) Z0/Z1 := (Result == 0) None. None.
MCU Team LSI Division System LSI Business
- 56 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
INCC
Increment with Carry
INCC Rn
Description
The INCC (Increment with Carry) instruction is used to synthesize 32-bit increment. If register pair R0, R1 holds a 32-bit value (R0 holds the leastsignificant word), the following instructions leave the 32-bit incremented value in R0, R1: INC R0 INCC R1 INCC increments the value of Rn by 1 only if the Carry flag (stored in the T bit) is set, and stores the result back in register Rn. The T bit and the V flag are updated based on the result. // will be replaced by ADD R0, 1
15
14
13
12
11
10
9
8
7
6
5
4
3
0
1
0
0
0
1
0
1
0
1
1
1
0
Rn
Operation
Rn := Rn + T bit T bit := Carry from (Rn + T bit) V flag := Overflow from (Rn + T bit) if(Rn == R6/R7) Z0/Z1 := ((Rn + T0) == 0)
Exceptions Notes
None. None.
MCU Team LSI Division System LSI Business
- 57 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
JMP (1)
Jump Register
JPF/JPT/JMP/JSR Ai
Description
The Jump Register instructions change the program flow by assigning the value of register Ai into PC. JPF and JPT are conditional jumps that check the T bit to determine whether or not to jump to the target address. JMP unconditionally jumps to the target. JSR is an unconditional jump but saves the return address (the immediately following instruction to JSR) in the link register, A14. At the end of each subroutine, JMP A14 will change the program flow back to the original call site.
15
14
13
12
11
10
9
8 M[1]
7
6
5
4
3 M[0]
2
0
1
0
0
0
0
1
1
1
1
1
0
Ai
Operation
(M == 00, JPF) if (T bit == FALSE) PC := Ai (M == 01, JPT) if (T bit == TRUE) PC := Ai (M == 10, JMP) PC := Ai (M == 11, JSR) A14 := PC + 2 PC := Ai
Exceptions Notes
None. There is no delay slot for these instructions. Therefore, when conditional branch JPF or JPT is taken, the instruction in the pipeline which is fetched from PC+2 will be squashed. In case of JMP and JSR (always taken), the following instruction fetched will be always squashed.
MCU Team LSI Division System LSI Business
- 58 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
JMP (2)
Jump Immediate
JPF/JPT/JMP/JSR
Description
The Jump Immediate instructions change the program flow by assigning the value of into PC. JPF and JPT are conditional jumps that check the T bit to determine whether or not to jump to the target address. JMP unconditionally jumps to the target. JSR is an unconditional jump but saves the return address (the immediately following instruction to JSR) in the link register, A14. At the end of each subroutine, JMP A14 will change the program flow back to the original call site.
15
14
13
12
11
10
9
8
7
6
5
0
1
0
0
1
1
1
1
1

[21:16]
Operation
( == 00, JPF) if (T bit == FALSE) PC := ( == 01, JPT) if (T bit == TRUE) PC := ( == 10, JMP) PC := ( == 11, JSR) A14 := PC + 4 PC :=
Exceptions Notes
None. These are 2-word instructions, where the 16-bit immediate ([15:0]) follows the instruction word shown above. As fetching of a 2-word instruction takes 2 cycles, no later instructions will be in processor pipeline when the branch is taken (thus no squashing).
MCU Team LSI Division System LSI Business
- 59 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
LD (1)
Load Register
LD Rn, Ri
Description
The LD (Load Register) instruction is used to transfer a register value to a register.
15
14
13
12
11
8
7
6
5
4
3
0
1
0
0
0 Rn := Ri
Rn
1
1
0
1
Ri
Operation Exceptions Notes
if(Rn == R6/R7) Z0/Z1 := (Ri == 0) None. None.
MCU Team LSI Division System LSI Business
- 60 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
LD (2)
Load Extended Register
LD An, Ai
Description
15 14 13
This form of LD instruction (Load Extended Register) is used to load a 22-bit register value to a 22-bit register.
12 11 10 9 8 7 6 5 4 3 0
1
0
1
0
1
An
0
0
0
1
1
Ai
Operation Exceptions Notes
An := Ai None. None.
MCU Team LSI Division System LSI Business
- 61 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
LD (3)
Load Short Immediate
LD Rn, #
Description
The LD (Load Short Immediate) instruction is used to load an 8-bit immediate value to a register.
15
14
13
12
11
8
7
0
0
0
0
1
Rn

Operation Exceptions Notes
Rn[15:8] := 0, Rn[7:0] := if(Rn == R6/R7) Z0/Z1 := ( == 0) None. None.
MCU Team LSI Division System LSI Business
- 62 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
LD (4)
Load Immediate
LD Rn, #
Description
This form of LD instruction (Load Immediate) is used to load a 16-bit immediate value to a register.
15
14
13
12
11
10
9
8
7
6
5
4
3
0
1
0
0
0
1
1
0
1
1
1
1
1
Rn
Operation Exceptions Notes
Rn := if(Rn == R6/R7) Z0/Z1 := ( == 0) None. This is a 2-word instruction, where the 16-bit immediate follows the instruction word shown above. Unlike 1-word instructions, therefore, fetching of this instruction takes 2 cycles.
MCU Team LSI Division System LSI Business
- 63 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
LD (5)
Load Large Immediate
LD An, #
Description
This form of LD instruction (Load Large Immediate) is used to load a 22-bit immediate value to an extended register An.
15
14
13
12
11
10
8
7
6
5
0
1
0
1
0
1
An
1
0
[21:16]
Operation Exceptions Notes
An := None. This is a 2-word instruction, where the 16-bit immediate ([15:0]) follows the instruction word shown above. Unlike 1-word instructions, therefore, fetching of this instruction takes 2 cycles.
MCU Team LSI Division System LSI Business
- 64 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
LD RExt
Load Register Extension
LD Dn, Ei / LD En, Di
Description
15 14 13
The LD RExt (Load Register Extension) instructions are used to transfer a register value to and from a 6-bit extension register.
12 11 8 7 6 5 4 3 2 0
1
0
1
0
0
Dn(or Di)
0
0
0
1
M
Ei (or En)
Operation
(M == 0, LD Dn, Ei) Dn := Ei (zero-extended to 16 bits) (M == 1, LD En, Di) En := Di (lower 6 bits only)
Exceptions Notes
None. None.
MCU Team LSI Division System LSI Business
- 65 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
LDB (1)
Load Byte Register Disp.
LDB Dn, @[Ai+] / LDB @[An+], Di
Description
The LDB (Load Byte Register Displacement) instruction is used to load a byte from or to data memory at the location specified by the register Ai and a 4-bit displacement.
15
14
13
12
11
10
8
7
6
4
3
0
0
1
1
M
0
Dn or Di
0
Ai or An

Operation
(M == 0, LDB Dn, @[Ai+]) Dn := DM[(Ai+)] (M == 1, LDB @[An+], Di) DM[(An+)] := Di
Exceptions Notes
None. None.
MCU Team LSI Division System LSI Business
- 66 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
LDB (2)
Load Byte Register Large Disp.
LDB Dn, @[Ai+] / LDB @[An+], Di
Description
The LDB (Load Byte Register Large Displacement) instruction is used to load a byte from or to data memory at the location specified by the register Ai and a 16bit displacement.
15
14
13
12
11
10
8
7
6
5
4
3
2
0
1
0
1
0
0
Dn or Di
0
0
1
1
M
Ai or An
Operation
(M == 0, LDB Dn, @[Ai+]) Dn := DM[(Ai+)] (M == 1, LDB @[An+], Di) DM[(An+)] := Di
Exceptions Notes
None. This is a 2-word instruction, where the 16-bit immediate follows the instruction word shown above. Unlike 1-word instructions, therefore, fetching of this instruction takes 2 cycles.
MCU Team LSI Division System LSI Business
- 67 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
LDB (3)
Load Byte Register Indexed
LDB Dn, @[Ai+Rj] / LDB @[An+Rm], Di
Description
The LDB (Load Byte Register Indexed) instruction is used to load a byte from or to data memory at the location specified by the register Ai (or An) and the second register Rj (or Rm).
15
14
13
12
11
10
8
7
6
4
3
0
0
1
1
M
0
Dn or Di
1
Ai or An
Rj or Rm
Operation
(M == 0, LDB Dn, @[Ai+Rj]) Dn := DM[(Ai+Rj] (M == 1, LDB @[An+Rm], Di) DM[(An+Rm)] := Di
Exceptions Notes
None. None.
MCU Team LSI Division System LSI Business
- 68 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
LDB (4)
Load Byte to R0 Register Disp.
LDB R0, @[A8+] / LDB @[A8+], A8
Description
The LDB (Load Byte to R0 Register Displacement) instruction is used to load a byte from or to data memory at the location specified by the register A8 and an 8bit displacement.
15
14
13
12
11
10
9
8
7
0
1
0
0
1
1
1
0
M

Operation
(M == 0, LDB R0, @[A8+]) R0 := DM[(A8+] (M == 1, LDB @[A8+], R0) DM[(A8+)] := R0
Exceptions Notes
None. This single-word instruction allows a user to access a wider range of data memory than the LDB (1) instruction by providing a larger displacement, at the expense of the restrictions that only the R0 and A8 registers are used for data transfer and address computation.
MCU Team LSI Division System LSI Business
- 69 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
LDC
Load Code
LDC Rn, @Ai
Description
The LDC instruction is used to transfer a register value from the program memory. The program memory address is specified by the 22-bit register An. LDC is useful to look up the data stored in program memory, such as the coefficient table for certain numerical algorithms.
15
14
13
12
11
8
7
6
5
4
3
2
0
1
0
1
0 Rn := PM[Ai] None. None.
Rn
0
0
0
0
0
Ai
Operation Exceptions Notes
MCU Team LSI Division System LSI Business
- 70 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
LD PC
Load Program Counter
LD An, PC
Description
The LD PC (Load Program Counter) instruction is used to transfer the value of PC into a 22-bit register An. This instruction provides a way to implement position independent code (PIC) on CalmRISC16 even in the absence of general virtual memory support. After executing this instruction, An will be used to compute a PC-relative location of a data item or a code section.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
1
0
0
1
1
1
1
0
1
1
1
1
0
An
Operation Exceptions Notes
An := PC + 4 None. None.
MCU Team LSI Division System LSI Business
- 71 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
LD SvR (1)
Load from Saved Register
LD R0, SPCL_* / LD R0, SPCH_* / LD R0, SSR_*
Description
The LD SvR (Load from Saved Register) instructions are used to transfer a value from the specified interrupt register, e.g., SSR_FIQ. Only R0 register is used for this data transfer.
15
14
13
12
11
10
9
8
7
6
5
4
3
0
1
0
0
1
1
1
1
0
1
0
1
0

Operation
R0 := Encoding for (Register Specifier): 0000: SPCL_FIQ, 0001: SPCH_FIQ, 0010: SSR_FIQ, 0100: SPCL_IRQ, 0101: SPCH_IRQ, 0110: SSR_IRQ, 1010: SSR_SWI
Exceptions Notes
None. None.
MCU Team LSI Division System LSI Business
- 72 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
LD SvR (2)
Load to Saved Register
LD SPCL_*, R0 / LD SPCH_*, R0 / LD SSR_*, R0
Description
The LD SvR (Load to Saved Register) instructions are used to transfer a value to the specified interrupt register, e.g., SSR_FIQ. Only R0 register is used for this data transfer.
15
14
13
12
11
10
9
8
7
6
5
4
3
0
1
0
0
1
1
1
1
0
1
0
1
1

Operation
:= R0 Encoding for (Register Specifier): 0000: SPCL_FIQ, 0001: SPCH_FIQ, 0010: SSR_FIQ, 0100: SPCL_IRQ, 0101: SPCH_IRQ, 0110: SSR_IRQ, 1010: SSR_SWI
Exceptions Notes
None. None.
MCU Team LSI Division System LSI Business
- 73 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
LD SR
Load Status Register
LD R0, SR / LD SR, R0
Description
The LD SR (Load Status Register) instruction is used to transfer a value to and from SR. Only R0 register is used for this operation.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
0
1
1
1
1
0
1
0
0
1
1
0
1
M
Operation
(M == 0, LD R0, SR) R0 := SR (M == 1, LD SR, R0) SR := R0
Exceptions Notes
None. None.
MCU Team LSI Division System LSI Business
- 74 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
LDW (1)
Load Word Stack Disp.
LDW Rn, @[SP+] / LDW @[SP+], Ri
Description
The LDW (Load Word Stack Displacement) instruction is used to load a word from or to data memory at the location specified by the SP register (or A15) and an even 9-bit displacement. , from 0 to 510, is encoded into 8-bit displacement by dropping the least significant bit.
15
14
13
12
11
8
7
0
0
0
1
M
Rn or Ri

Operation
(M == 0, LDW Rn, @[SP+]) Rn := DM[(SP + )] (M == 1, LDW @[SP+], Ri) DM[(SP + )] := Ri
Exceptions Notes
None. For memory transfer per word, the (byte) address need to be aligned to be even. Thus, if (SP + ) is an odd number, it will be made even by clearing the least significant bit. can denote an even number from 0 to 510.
MCU Team LSI Division System LSI Business
- 75 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
LDW (2)
Load Word Register Small Disp.
LDW Rn, @[Ai+] / LDW @[An+], Ri
Description
The LDW (Load Word Register Displacement) instruction is used to load a word from or to data memory at the location specified by the register Ai and a 5-bit even displacement from 0 to 30. is encoded to 4-bit number by dropping the least significant bit.
15
14
13
12
11
8
7
6
4
3
0
0
1
0
M
Rn or Ri
0
Ai or An

Operation
(M == 0, LDW Rn, @[Ai+]) Rn := DM[(Ai + )] (M == 1, LDW @[An+], Ri) DM[(An + )] := Ri
Exceptions Notes
None. For memory transfer per word, the (byte) address need to be aligned to be even. Thus, if (Ai + ) is an odd number, it will be made even by clearing the least significant bit. can denote an even number from 0 to 30.
MCU Team LSI Division System LSI Business
- 76 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
LDW (3)
Load Word Register Disp.
LDW Rn, @[Ai+] / LDW @[An+], Ri
Description
The LDW (Load Word Register Large Displacement) instruction is used to load a word from or to data memory at the location specified by the register Ai and a 16bit displacement.
15
14
13
12
11
8
7
6
5
4
3
2
0
1
0
1
0
Rn or Ri
0
0
1
0
M
Ai or An
Operation
(M == 0, LDW Rn, @[Ai+]) Rn := DM[(Ai + )] (M == 1, LDW @[An+], Ri) DM[(An + )] := Ri
Exceptions Notes
None. This is a 2-word instruction, where the 16-bit immediate follows the instruction word shown above. Unlike 1-word instructions, therefore, fetching of this instruction takes 2 cycles. For memory transfer per word, the (byte) address need to be aligned to be even. Thus, if (Ai + ) is an odd number, it will be made even by clearing the least significant bit.
MCU Team LSI Division System LSI Business
- 77 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
LDW (4)
Load Word Register Indexed
LDW Rn, @[Ai+Rj] / LDW @[An+Rm], Ri
Description
The LDW (Load Word Register Indexed) instruction is used to load a word from or to data memory at the location specified by the register Ai (or An) and the second register Rj (or Rm), which is an unsigned value.
15
14
13
12
11
8
7
6
4
3
0
0
1
0
M
Rn or Ri
1
Ai or An
Rj or Rm
Operation
(M == 0, LDW Rn, @[Ai+Rj]) Rn := DM[(Ai+Rj] (M == 1, LDW @[An+Rm], Ri) DM[(An+Rm)] := Ri
Exceptions Notes
None. For memory transfer per word, the (byte) address needs to be aligned to be even. Thus, if (Ai + Rj) or (An + Rm) is an odd number, it will be made even by clearing the least significant bit.
MCU Team LSI Division System LSI Business
- 78 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
LDW (5)
Load Word Register Small Disp.
LDW An, @[Ai+] / LDW @[Ai+], An
Description
The LDW (Load Word Register Displacement) instruction is used to load 2 word from or to data memory at the location specified by the register Ai and a 5-bit even displacement from 0 to 30. is encoded to 4-bit number by dropping the least significant bit.
15
14
13
12
11
8
7
6
4
3
0
0
1
1
M
1
An
0
Ai

Operation
(M == 0, LDW An, @[Ai+]) En := DM[(Ai + )] Rn := DM[(Ai + + 2)] (M == 1, LDW @[Ai+], An) DM[(Ai + )] := En DM[(Ai + + 2)] := Rn
Exceptions Notes
None. For memory transfer per word, the (byte) address need to be aligned to be even. Thus, if (Ai + ) is an odd number, it will be made even by clearing the least significant bit. can denote an even number from 0 to 30.
MCU Team LSI Division System LSI Business
- 79 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
LDW (6)
Load Word Register Disp.
LDW An, @[Ai+] / LDW @[Ai+], An
Description
The LDW (Load Word Register Large Displacement) instruction is used to load 2 word from or to data memory at the location specified by the register Ai and a 16bit displacement.
15
14
13
12
11
8
7
6
5
4
3
2
0
1
0
1
0
1
An
0
0
1
1
M
Ai
Operation
(M == 0, LDW An, @[Ai+]) En := DM[(Ai + )] Rn := DM[(Ai + + 2)] (M == 1, LDW @[Ai+], An) DM[(Ai + )] := En DM[(Ai + + 2)] := Rn
Exceptions Notes
None. This is a 2-word instruction, where the 16-bit immediate follows the instruction word shown above. Unlike 1-word instructions, therefore, fetching of this instruction takes 2 cycles. For memory transfer per word, the (byte) address need to be aligned to be even. Thus, if (Ai + ) is an odd number, it will be made even by clearing the least significant bit.
MCU Team LSI Division System LSI Business
- 80 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
LDW (7)
Load Word Register Indexed
LDW An, @[Ai+Rj] / LDW @[Ai+Rj], An
Description
The LDW (Load Word Register Indexed) instruction is used to load 2 word from or to data memory at the location specified by the register Ai and the second register Rj, which is an unsigned value.
15
14
13
12
11
8
7
6
4
3
0
0
1
1
M
1
An
1
Ai
Rj
Operation
(M == 0, LDW An, @[Ai + Rj]) En := DM[(Ai + Rj)] Rn := DM[(Ai + Rj + 2)] (M == 1, LDW @[Ai + Rj], An) DM[(Ai + Rj)] := En DM[(Ai + Rj + 2)] := Rn
Exceptions Notes
None. For memory transfer per word, the (byte) address needs to be aligned to be even. Thus, if (Ai + Rj) is an odd number, it will be made even by clearing the least significant bit.
MCU Team LSI Division System LSI Business
- 81 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
MUL
Multiplication
MUL Mode, Dn, Di
Description
The instruction MUL performs 8x8 multiplication of the least significant byte of Dn and the least significant byte of Di. Dn and Di are registers from R0 to R7. The 16-bit multiplication result is written back to Dn. The mode is one of UU, US, SU, SS. The mode indicates each operand is signed value or unsigned value.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
1
0
M1
Dn
1
1
0
1
M2
Di
Operation
if(M1 == 0 && M2 == 0) else if(M1 == 0 && M2 == 1) else if(M1 == 1 && M2 == 0) else // mode == SS
// mode = UU // mode == US // mode == SU
Dn := lower 16 bits of ({0,Dn[7:0]} * {0, Di[7:0]}) Dn := lower 16 bits of ({0,Dn[7:0]} * {Di[7],Di[7:0]}) Dn := lower 16 bits of ({Dn[7],Dn[7:0]} * {0,Di[7:0]}) Dn := lower 16 bits of ({Dn[7],Dn[7:0]} * {Di[7],Di[7:0]})
Exceptions Notes
None. None.
MCU Team LSI Division System LSI Business
- 82 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
NOP
No Operation
NOP
Description
The NOP (No Operation) instruction does not perform any operation.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
0
1 None. None. None.
1
1
1
0
1
0
0
1
0
0
0
0
Operation Exceptions Notes
MCU Team LSI Division System LSI Business
- 83 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
OR (1)
OR Register
OR Rn, Ri
Description
The OR (OR Register) instruction is used to perform bitwise OR operation on two values in registers, Rn and Ri. The result is stored in register Rn. The T bit is updated based on the result.
15
14
13
12
11
8
7
6
5
4
3
0
1
0
0
0 Rn := Rn | Ri
Rn
0
1
0
1
Ri
Operation
T bit := ((Rn | Ri) == 0) if(Rn == R6/R7) Z0/Z1 := ((Rn|Ri) == 0)
Exceptions Notes
None. None.
MCU Team LSI Division System LSI Business
- 84 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
OR (2)
OR Small Immediate
OR R0, #
Description
The OR (OR Small Immediate) instruction is used to perform bitwise OR operation on two values in register R0 and . The result is stored in register R0. The T bit is updated based on the result.
15
14
13
12
11
10
9
8
7
0
1
0
0
1
1
0
0
1

Operation Exceptions Notes
R0 := R0 | T bit := ((R0 | )[7:0] == 0) None. The register used in this operation is fixed to R0. Therefore, the operand should be placed in R0 before this instruction executes. is zero-extended to a 16-bit value before operation.
MCU Team LSI Division System LSI Business
- 85 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
OR (3)
OR Large Immediate
OR Rn, #
Description
This type of OR instruction is used to perform bitwise OR operation on two values in register Rn and . The result is stored in register R0. The T bit is updated based on the result.
15
14
13
12
11
10
9
8
7
6
5
4
3
0
1
0
0
0
0
1
0
1
1
1
1
1
Rn
Operation
Rn := Rn | T bit := ((Rn | ) == 0) if(Rn == R6/R7) Z0/Z1 := ((Rn | ) == 0)
Exceptions Notes
None. This is a 2-word instruction, where the 16-bit immediate follows the instruction word shown above. Unlike 1-word instructions, therefore, fetching of this instruction takes 2 cycles.
MCU Team LSI Division System LSI Business
- 86 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
POP(1)
Load register from Stack
POP Rn, Rm / POP Rn
Description
The POP instruction load one or two 16-bit data from software stack to general registers. In the instruction of "POP Rn, Rm", there are some restrictions on Rn and Rm. Rn and Rm should not be R15. If Rn is one of the 8 registers from R0 to R7, Rm should also be one of them. If Rn is one of the registers from R8 to R14, Rm should also be one of them. For example, "POP R7, R8" is illegal. If Rn is the same as Rm, pop operation occurs only once. "POP Rn, Rn" is equivalent to "POP Rn".
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
1
0 if(Rn == Rm) { SP := SP + 2 } else {
Rm // POP Rn
1
1
1
0
0
Rn
Operation
Rn := DM[SP + 2]
Rn := DM[SP + 2] Rm := DM[SP + 4] SP := SP + 4 }
Exceptions Notes
None. None.
MCU Team LSI Division System LSI Business
- 87 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
POP(2)
Load register from Stack
POP An, Am / POP An
Description
The POP instruction load one or two 22-bit data from software stack to extended registers. In the instruction of "POP An, Am", there are some restrictions on An and Am. An and Am should not be A15. If An is the same as Am, pop operation occurs only once. "POP An, An" is equivalent to "POP An".
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
1
0
1
Am // POP An
1
1
1
0
1
An
Operation
if(An == Am) {
En := lower 6 bits of DM[SP + 2] Rn := DM[SP + 4] SP := SP + 4 } else { En := lower 6 bits of DM[SP + 2] Rn := DM[SP + 4] Em := lower 6 bits of DM[SP + 6] Rm := DM[SP + 8] SP := SP + 8 }
Exceptions Notes
None. None.
MCU Team LSI Division System LSI Business
- 88 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
PUSH(1)
Load register to Stack
PUSH Rn, Rm / PUSH Rn
Description
The PUSH instruction load one or two 16-bit data from general registers to software stack. In the instruction of "PUSH Rn, Rm", there are some restrictions on Rn and Rm. Rn and Rm should not be R15. If Rn is one of the 8 registers from R0 to R7, Rm should also be one of them. If Rn is one of the registers from R8 to R14, Rm should also be one of them. For example, "PUSH R7, R8" is illegal. If Rn is the same as Rm, push operation occurs only once. "PUSH Rn, Rn" is equivalent to "PUSH Rn".
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
1
0 if(Rn == Rm) {
Rm // PUSH Rn
1
1
1
1
0
Rn
Operation
DM[SP] := Rn SP := SP - 2 } else { DM[SP] := Rn DM[SP - 2] := Rm SP := SP - 4 }
Exceptions Notes
None. None.
MCU Team LSI Division System LSI Business
- 89 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
PUSH(2)
Load register to Stack
PUSH An, Am / PUSH An
Description
The PUSH instruction load one or two 22-bit data to software stack from extended registers. In the instruction of "PUSH An, Am", there are some restrictions on An and Am. An and Am should not be A15. If An is the same as Am, push operation occurs only once. "PUSH An, An" is equivalent to "PUSH An".
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
1
0
1
Am // PUSH An
1
1
1
1
1
An
Operation
if(An == Am) { DM[SP] := Rn
DM[SP - 2] := {10'h000, En} SP := SP - 4 } else { DM[SP] := Rn DM[SP - 2] := {10'h000, En} DM[SP - 4] := Rm DM[SP - 6] := {10'h000, Em} SP := SP - 8 }
Exceptions Notes
None. None.
MCU Team LSI Division System LSI Business
- 90 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
RETD
Ret. from Subroutine with Delay Slot
RETD
Description
The RETD (Return from Subroutine with Delay Slot) instruction is used to finish a subroutine and return by jumping to the address specified by the link register or A14. The difference between RETD and JMP A14 is that RETD has a delay slot, which allows efficient implementation of small subroutines.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
0
1
1
1
1
0
1
0
0
1
1
1
1
1
Operation Exceptions Notes
PC := A14
None. None.
MCU Team LSI Division System LSI Business
- 91 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
RET_FIQ
Return from Fast Interrupt
RET_FIQ
Description
The RET_FIQ (Return from Fast Interrupt) instruction is used to finish a FIQ handler and resume the normal program execution. When this instruction is executed, SSR_FIQ (saved SR) is restored into SR, and the program control transfers to (SPCH_FIQ:SPCL_FIQ).
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
0
1
1
1
1
0
1
0
0
1
1
1
0
0
Operation Exceptions Notes
SR := SSR_FIQ PC := (SPCH_FIQ:SPCL_FIQ) None. Fast Interrupt is requested through the core signal nFIQ. When the request is acknowledged, SR and current PC are saved in the designated registers (namely SSR_FIQ and SPCH_FIQ:SPCL_FIQ) assigned for FIQ processing. Such bits in SR as FE, IE, and TE are cleared, and PM is set.
MCU Team LSI Division System LSI Business
- 92 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
RET_IRQ
Return from Interrupt
RET_IRQ
Description
The RET_IRQ (Return from Interrupt) instruction is used to finish an IRQ handler and resume the normal program execution. When this instruction is executed, SSR_IRQ (saved SR) is restored into SR, and the program control transfers to (SPCH_IRQ:SPCL_IRQ).
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
0
1
1
1
1
0
1
0
0
1
1
1
0
1
Operation Exceptions Notes
SR := SSR_IRQ PC := (SPCH_IRQ:SPCL_IRQ) None. Interrupt is requested through the core signals nIRQ. When the request is acknowledged, SR and current PC are saved in the designated registers (namely SSR_IRQ and SPCH_FIQ:SPCL_IRQ) assigned for IRQ processing. Such bits in SR as IE and TE are cleared, and PM is set.
MCU Team LSI Division System LSI Business
- 93 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
RET_SWI
Return from Software Interrupt
RET_SWI
Description
The RET_SWI (Return from Software Interrupt) instruction is used to finish a SWI handler and resume the normal program execution. When this instruction is executed, SSR_FIQ (saved SR) is restored into SR, and the program control transfers to the address A14 (link register).
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
0
1
1
1
1
0
1
0
0
1
1
1
1
0
Operation Exceptions Notes
SR := SSR_SWI PC := A14 None. Software interrupt is initiated by executing a SWI instruction from applications. When SWI instruction is executed, SR and current PC are saved in the designated registers (namely SSR_SWI and A14) assigned for SWI processing.
MCU Team LSI Division System LSI Business
- 94 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
RL
Rotate Left
RL Rn
Description
The RL (Rotate Left) instruction rotates the value of Rn left by one bit and stores the result back in Rn. T bit is updated as a result of this operation.
15
14
13
12
11
10
9
8
7
6
5
4
3
0
1
0
0
0
0
0
0
1
1
1
1
0
Rn
Operation Exceptions Notes
Rn := Rn << 1, Rn[0] = MSB of Rn before rotation T bit := MSB of Rn before rotation None. None.
MCU Team LSI Division System LSI Business
- 95 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
RR
Rotate Right
RR Rn
Description
The RR (Rotate Right) instruction rotates the value of Rn right by one bit and stores the result back in Rn. T bit is updated as a result of this operation.
15
14
13
12
11
10
9
8
7
6
5
4
3
0
1
0
0
0
0
0
0
0
1
1
1
0
Rn
Operation Exceptions Notes
Rn := Rn >> 1, MSB of Rn = Rn[0] before rotation T bit := Rn[0] before rotation None. None.
MCU Team LSI Division System LSI Business
- 96 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
RRC
Rotate Right with Carry
RRC Rn
Description
The RRC (Rotate Right with Carry) instruction rotates the value of (Rn:T bit) right by one bit and stores the result back in Rn. T bit is updated as a result of this operation.
15
14
13
12
11
10
9
8
7
6
5
4
3
0
1
0
0
0
0
0
1
0
1
1
1
0
Rn
Operation Exceptions Notes
Rn := Rn >> 1, MSB of Rn = T bit before rotation T bit := Rn[0] before rotation None. None.
MCU Team LSI Division System LSI Business
- 97 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
SBC (1)
Subtract with Carry Register
SBC Rn, Ri
Description
The SBC (Subtract with Carry) instruction is used to synthesize 32-bit subtraction. If register pairs R0, R1 and R2, R3 hold 32-bit values (R0 and R2 hold the leastsignificant word), the following instructions leave the 32-bit result in R0, R1: SUB R0, R2 SBC R1, R3 SBC subtracts the value of register Ri, and the value of the Carry flag (stored in the T bit), from the value of register Rn, and stores the result in register Rn. The T bit and the V flag are updated based on the result.
15
14
13
12
11
8
7
6
5
4
3
0
1
0
0
0
Rn
0
0
1
1
Ri
Operation
Rn := Rn + ~Ri + T bit T bit := Carry from (Rn + ~Ri + T bit) V flag := Overflow from (Rn + ~Ri + T bit) if(Rn == R6/R7) Z0/Z1 := ((Rn + ~Ri + T) == 0)
Exceptions Notes
None. None.
MCU Team LSI Division System LSI Business
- 98 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
SBC (2)
Subtract with Carry Immediate
SBC Rn, #
Description
The SBC (Subtract with Carry immediate) instruction is used to synthesize 32-bit subtraction with an immediate operand. If register pair R0, R1 holds a 32-bit value (R0 holds the least-significant word), the following instructions leave the 32-bit subtraction result with 34157856h in R0, R1: SUB R0, #7856h SBC R1, #3415h SBC subtracts the value of , and the value of the Carry flag (stored in the T bit), from the value of Rn, and stores the result in register Rd. The T bit and the V flag are updated based on the result.
15
14
13
12
11
10
9
8
7
6
5
4
3
0
1
0
0
0
0
0
1
1
1
1
1
1
Rn
Operation
Rn := Rn + ~ + T bit T bit := Carry from (Rn + ~ + T bit) V flag := Overflow from (Rn + ~ + T bit) if(Rn == R6/R7) Z0/Z1 := ((Rn + ~ + T) == 0)
Exceptions Notes
None. This is a 2-word instruction, where the 16-bit immediate follows the instruction word shown above. Unlike 1-word instructions, therefore, fetching of this instruction takes 2 cycles.
MCU Team LSI Division System LSI Business
- 99 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
SETSR
Set SR
SETSR bs:3
Description
The SETSR (Set SR) instruction is used to set a specified bit in SR as follows: SETSR FE / IE / TE / V / Z0 / Z1 / PM To set the T bit, one can do as follows: CMP EQ, R0, R0 To clear a specified bit in SR, the CLRSR instruction (in page 45) is used.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
1
0
0
1
1
1
1
0
1
0
0
0
1

Operation Exceptions Notes
SR[] := 1 None. None.
MCU Team LSI Division System LSI Business
- 100 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
SR
Shift Right
SR Rn
Description
The SR (Shift Right) instruction shifts the value of Rn right by one bit and stores the result back in Rn. T bit is updated as a result of this operation.
15
14
13
12
11
10
9
8
7
6
5
4
3
0
1
0
0
0
0
1
0
0
1
1
1
0
Rn
Operation Exceptions Notes
Rn := Rn >> 1, with Rn[15] set to 0 T bit := Rn[0] before shifting None. None.
MCU Team LSI Division System LSI Business
- 101 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
SRA
Shift Right Arithmetic
SRA Rn
Description
The SRA (Shift Right Arithmetic) instruction shifts the value of Rn right by one bit and stores the result back in Rn. While doing so, the original sign bit (most significant bit) is copied to the most significant bit of the result. T bit is updated as a result of this operation.
15
14
13
12
11
10
9
8
7
6
5
4
3
0
1
0
0
0
0
1
0
1
1
1
1
0
Rn
Operation
Rn := Rn >> 1, with Rn[15] set to the original value T bit := Rn[0] before shifting
Exceptions Notes
None. None.
MCU Team LSI Division System LSI Business
- 102 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
SRB
Shift Right Byte
SRB Rn
Description
The SRB (Shift Right Byte) instruction shifts the value of Rn right by 8 bit and stores the result back in Rn. The high 8 bit positions are filled with 0's. T bit is updated as a result of this operation.
15
14
13
12
11
10
9
8
7
6
5
4
3
0
1
0
0
0
0
0
1
1
1
1
1
0
Rn
Operation
Rn[7:0] := Rn[15:8] and Rn[15:8] := 8'h00 T bit := Rn[7] before shifting
Exceptions Notes
None. None.
MCU Team LSI Division System LSI Business
- 103 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
SUB (1)
Subtract Register
SUB Rn, Ri
Description
The SUB (Subtract Register) instruction is used to subtract a 16-bit register value from another 16-bit register value. 32-bit subtraction can be achieved by executing SBC instruction in pair with this instruction (see page 98). SUB subtracts the value of register Ri from the value of Rn, and stores the result in register Rn. The T bit and the V flag are updated based on the result.
15
14
13
12
11
8
7
6
5
4
3
0
1
0
0
0 Rn := Rn - Ri
Rn
0
0
0
1
Ri
Operation
T bit := Carry from (Rn - Ri) V flag := Overflow from (Rn - Ri) if(Rn == R6/R7) Z0/Z1 := ((Rn - Ri) == 0)
Exceptions Notes
None. None.
MCU Team LSI Division System LSI Business
- 104 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
SUB (2)
Subtract Small Immediate
SUB Rn, #
Description
This form of SUB instruction is used to subtract a 7-bit immediate value from a register It subtracts the value of from the value of register Rn, and stores the result in register Rn. The T bit and the V flag is updated based on the result.
15
14
13
12
11
8
7
6
0
0
0
0
0
Rn
1

Operation
Rn := Rn - T bit := Carry from (Rn - ) V flag := Overflow from (Rn - ) if(Rn == R6/R7) Z0/Z1 := ((Rn - ) == 0)
Exceptions Notes
None. is an unsigned amount.
MCU Team LSI Division System LSI Business
- 105 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
SUB (3)
Subtract Extended Register
SUB An, Ri
Description
This form of SUB instruction (Subtract Extended Register) is used to add a 16-bit unsigned register value from a 22-bit value in register. This instruction subtracts the value of 16-bit register Ri from the value of 22-bit register An, and stores the result in register An.
15
14
13
12
11
10
8
7
6
5
4
3
0
1
0
1
0
1
An
1
1
0
0
Ri
Operation Exceptions Notes
An := An - Ri None. None.
MCU Team LSI Division System LSI Business
- 106 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
SUB (4)
Subtract Large Immediate
SUB An, #
Description
The SUB (Subtract Large Immediate) instruction is used to subtract a 16-bit unsigned immediate value from a 22-bit register. SUB subtracts the value of from the value of An, and stores the result in register An.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
1
0
0
0
0
0
0
1
1
1
1
1
1
An
Operation Exceptions Notes
An := An - None. This is a 2-word instruction, where the 16-bit immediate follows the instruction word shown above. Unlike 1-word instructions, therefore, fetching of this instruction takes 2 cycles.
MCU Team LSI Division System LSI Business
- 107 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
SUB (5)
Subtract 5-bit Immediate
SUB An, #
Description
This form of SUB instruction (Subtract Extended Register) is used to subtract a 5bit unsigned immediate value from a 22-bit register. This instruction subtracts the value of 5-bit immediate from the value of 22-bit register An, and stores the result in register An.
15
14
13
12
11
10
8
7
6
5
4
0
1
0
1
0
1
An
0
1
1

Operation Exceptions Notes
An := An - None. None.
MCU Team LSI Division System LSI Business
- 108 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
SWI
Software Interrupt
SWI #
Description
The SWI (Software Interrupt) instruction performs a specified set of operations (i.e., an SWI handler). This instruction can be used as an interface to the low-level system software such as operating system. Executing this instruction is similar to performing a function call. However, interrupts (IRQ and TRQ) will be masked off so that when a software interrupt is handled, it can be seen as an uninterruptible operation. Note that FIQ can still be triggered when an SWI is serviced. Return from a SWI handler is done by RET_SWI unlike normal function calls.
15
14
13
12
11
10
9
8
7
6
5
0
1
0
0
1
1
1
1
0
0
1

Operation
A14 := PC + 2 SSR_SWI := SR IE := 0, TE := 0 PC := << 2
Exceptions Notes
None. Program addresses from 000000h to 0000feh are reserved for SWI handlers. SWI vectors 0 and 1 are not used, as the addresses from 000000h to 000007h are reserved for other interrupts.
MCU Team LSI Division System LSI Business
- 109 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
SYS
System
SYS #
Description
The SYS (System) instruction is used for system peripheral interfacing using DA[4:0] and nSYSID core signals.
15
14
13
12
11
10
9
8
7
6
5
4
0
1
0
0
1
1
1
1
0
0
0
1

Operation
core output signal DA[4:0] := , DA[21:5] := (unchanged) core output signal nSYSID := LOW
Exceptions Notes
None. None.
MCU Team LSI Division System LSI Business
- 110 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
TST (1)
Test Register
TST Rn, Ri
Description
The TST (TST Register) instruction is used to determine if many bits of a register are all clear, or if at least one bit of a register is set. TST performs a comparison by logically ANDing the value of register Rn with the value of Ri. T bit is set according to the result.
15
14
13
12
11
8
7
6
5
4
3
0
1
0
0
0
Rn
0
1
1
1
Ri
Operation Exceptions Notes
Temp := Rn & Ri T bit := ((Rn & Ri) == 0) None. None.
MCU Team LSI Division System LSI Business
- 111 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
TST (2)
Test Small Immediate
TST R0, #
Description
This type of TST instruction is used to determine if many bits of a register are all clear, or if at least one bit of a register is set. TST performs a comparison by logically ANDing the value of register Rn with the value of Ri. T bit is set according to the result.
15
14
13
12
11
10
9
8
7
0
1
0
0
1
1
0
1
1

Operation Exceptions Notes
Temp n := Rn & T bit := ((Rn & )[7:0] == 0) None. The register used in this operation is fixed to R0. Therefore, the operand should be placed in R0 before this instruction executes.
MCU Team LSI Division System LSI Business
- 112 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
TST (3)
Test Large Immediate
TST Rn, #
Description
This type of TST instruction is used to determine if many bits of a register are all clear, or if at least one bit of a register is set. TST performs a comparison by logically ANDing the value of register Rn with the value of Ri. T bit is set according to the result.
15
14
13
12
11
10
9
8
7
6
5
4
3
0
1
0
0
0
0
1
1
1
1
1
1
1
Rn
Operation Exceptions Notes
Temp := Rn & T bit := ((Rn & ) == 0) None. This is a 2-word instruction, where the 16-bit immediate follows the instruction word shown above. Unlike 1-word instructions, therefore, fetching of this instruction takes 2 cycles.
MCU Team LSI Division System LSI Business
- 113 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
TSTSR
Test SR
TSTSR bs:3
Description
The TSTSR (Test SR) instruction is used to test a specified bit in SR as the following example shows: TST FE / IE / TE / V / Z0 / Z1 / PM To set or clear a specified bit, the SETSR (in page 100) or CLRSR (in page 45) instruction is used.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
1
0
0
1
1
1
1
0
1
0
0
1
0

Operation Exceptions Notes
T bit := ~SR[] None. None.
MCU Team LSI Division System LSI Business
- 114 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
XOR (1)
XOR Register
XOR Rn, Ri
Description
The XOR (XOR Register) instruction is used to perform bitwise XOR operation on two values in registers, Rn and Ri. The result is stored in register Rn. The T bit is updated based on the result.
15
14
13
12
11
8
7
6
5
4
3
0
1
0
0
0 Rn = Rn ^ Ri
Rn
0
1
1
0
Ri
Operation
T bit = ((Rn ^ Ri) == 0) if(Rn == R6/R7) Z0/Z1 := ((Rn^Ri) == 0)
Exceptions Notes
None. None.
MCU Team LSI Division System LSI Business
- 115 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
XOR (2)
XOR Small Immediate
XOR R0, #
Description
This type of XOR instruction is used to perform bitwise XOR operation on two values in register R0 and . The result is stored in register R0. The T bit is updated based on the result.
15
14
13
12
11
10
9
8
7
0
1
0
0
1
1
0
1
0

Operation Exceptions Notes
R0 = R0 ^ T bit = ((R0 ^ )[7:0] == 0) None. The register used in this operation is fixed to R0. Therefore, the operand should be placed in R0 before this instruction executes. is zero-extended to a 16-bit value before operation.
MCU Team LSI Division System LSI Business
- 116 -
April 2000
Excellence in Low-Power
The way MCU/DSP should be
CalmRISC16 Reference Manual
XOR (3)
XOR Large Immediate
XOR Rn, #
Description
This type of XOR instruction is used to perform bitwise XOR operation on two values in register Rn and . The result is stored in register Rn. The T bit is updated based on the result.
15
14
13
12
11
10
9
8
7
6
5
4
3
0
1
0
0
0
0
1
1
0
1
1
1
1
Rn
Operation
Rn = Rn ^ T bit = ((Rn ^ ) == 0) if(Rn == R6/R7) Z0/Z1 := ((Rn^) == 0)
Exceptions Notes
None. This is a 2-word instruction, where the 16-bit immediate follows the instruction word shown above. Unlike 1-word instructions, therefore, fetching of this instruction takes 2 cycles.
MCU Team LSI Division System LSI Business
- 117 -
April 2000
S5L840F (Preliminary Spec)
CLOCK & POWER MANAGEMENT
5
CLOCK & POWER MANAGEMENT
OVERVIEW
The clock & power management unit consists of clock control, power control and reset control. The clock control logic in S5L840F generates various system clock signals: HCLK_CPU for CPU, HCLK for the AHB bus peripherals and PCLK for the APB bus peripherals. The clock control logic allows bypassing of PLL for slow clock and connection/disconnection of the clock to each peripheral block by software, which results in power reduction. Also, S5L840F has the power control logic to support various power management schemes for optimal power consumption for a given application. The power management provides five power modes: NORMAL mode, SLOW mode, IDLE mode, STANDBY mode and STOP mode. In NORMAL mode clock is supplied to CPU as well as all peripherals in S5L840F. The power consumption will be a maximum when all peripherals are turned on. Also, user is allowed to control supply of the clock to peripherals by software. For example, if user does not need timer and DMA, user can disconnect the clock to timer and DMA to reduce the power consumption. The SLOW mode is a non-PLL mode. Only difference to NORMAL mode is that the SLOW mode uses the external clock as a master clock in S5L840F rather than the internal PLL clock. In this case, the power consumed by PLL itself is eliminated, and the power consumption will depend on the frequency of the external clock. The IDLE mode disconnects the clock to CPU core while maintaining the clock to all peripherals. By using this IDLE mode, we can further reduce the power consumption by the CPU core. The wake-up from IDLE mode is done by an interrupt request to CPU. STOP mode freezes all clocks to the CPU as well as peripherals by disabling PLLs. The power consumption is only due to the leakage current in S3C2400, which is uA unit. The wake-up from STOP mode can be done by activating external interrupt pins. The reset controller in S5H5002 consists of three reset types: hardware reset, software reset and watchdog reset. These types of reset are described in detail on page 6-9 Reset Controller. FEATURE * * * * * Input frequency : 32.768 KHz. Output frequency range : 20MHz - 100MHz. Programmable frequency divider Power management : Normal, Slow, Idle, Standby and Stop. Reset controller : Hardware, Software, and Watchdog reset.
6-1
CLOCK & POWER MANAGEMENT
S5L840F (Preliminary Spec)
FUNCTION DESCRIPTION
CLOCK GENERATION Figure 6-1 shows a block diagram of the clock generator. An external crystal clock is connected to the oscillation amplifier, and the PLL (Phase-Locked-Loop) converts the low input frequency into a high-frequency clock required by S5L840F. The clock generator block also has a built-in logic to stabilize the clock frequency after each system reset since the clock takes time before stabilized. MAXIMUM BUS FREQUENCIES Table 6-1 lists the maximum operating frequencies for the S5L840F. When selecting strap settings, make sure that the bus divider ratios do not result in the bus frequencies that exceed these maximums. Table 6-1. Maximum Bus Frequencies Internal Bus AHB APB Maximum Frequency 100MHz 100MHz Module on the Internal Bus CPU Core, I/D cache, DMA,Interrupt,Clock & Power, Memory controller IIC, GPIO, UART, Timer, RTC, IIS, Watchdog timer. Symbol HCLK PCLK
6-2
S5H5002 RISC MICROPROCESSOR (Preliminary Spec)
CLOCK & POWER MANAGEMENT
debug_region = debug_entry | debug_mode
hclk_sel[1:0]
tclk
0 1
1'bx
0 1 2 3
pclk_div[3:0] pclk_div_on
hclk
PLL0
4-bit Prescaler
pclk
OSC
mclk_sel[1:0]
mclk_div[3:0] mclk_div_on
STOP
PLL0
1'bx
0 1 2 3
MCLK fine-tuner
4-bit Prescaler
mclk
uclk_sel[1:0]
1'bx
0 1 2 3
uclk
rclk
Figure 6-1. Clock Generator Block Diagram
NOTE Until PLLPMS register is configured for desired clock frequency by user, OSC clock (Fin) is supplied to the system.
6-3
CLOCK & POWER MANAGEMENT
S5L840F (Preliminary Spec)
PLL (PHASE LOCKED LOOP) The PLL in the clock generator synchronizes the output signal with the input reference signal in terms of frequency as well as phase. The output clock frequency Fpllo is related to the reference input clock frequency Fin by the following equation: Fpllo = Fin * (m + 1) / 2(s+1) m = M (the value for divider M)+ 8, p = P(the value for divider P) + 2
Change PLL Settings in Normal Operation Mode During the operation of S5L840F in NORMAL mode, if users want to change the frequency by modifying PMS value, the PLL lock time is automatically inserted. During the lock time, the clock will not be supplied to internal blocks in S5L840F. The timing diagram is as follow.
Fpllo PMS setting PLL lock time HCLK It changes to new PLL clock after lock time automatically
Figure 6-2. Timing Diagram of Clock Change in NORMAL Mode
6-4
S5H5002 RISC MICROPROCESSOR (Preliminary Spec)
CLOCK & POWER MANAGEMENT
POWER MANAGEMENT All clock signals for each AHB and APB device can be maskable. The CPU controls each of the clocks to enable or disable it to perform local power management. The CPU itself have it's own clock to be masked to enter IDLE mode which is one of the power saveing mode of S5L840F and can be woken up by interrupt. Including IDLE power saving mode S5L840F provides 4 global power saving modes which are SLOW, IDLE, STANBY, and STOP. NORMAL Mode : All clocks are alive. SLOW Mode : Non-PLL mode. Unlike the Normal mode, the Slow mode uses an X-tal oscillator directly as hclk_cpu in the S5L840F without PLL. In this mode, the power consumption depends on the frequency of the external clock only. The power consumption due to PLL is excluded. This is mainly for the purpose of displaying time on the LCD screen while the mp3 player is not operating. To display the time the CPU needs to be engaged but it doesn't need to run as fast as it runs to play audio. The CPU, RTC, and a number of peripherals are needed to run and display time on an LCD and they are required to operate with the X-tal frequency to consume minimun power. And all other pheriphrals that doesn't need to operate are powered-down by having their clocks masked. The X-tal frequency should be 32.768kHz for the real time clock. To further reduce the power consumption in this case, the CPU may be in IDLE mode and woken-up , so to speak, at every 0.5sec to update the time display on the LCD while the RTC operates always.
IDLE Mode : The CPU can mask it's own clock , hclk_cpu to enter IDLE mode and later interrupt input (nIRQ or nFIQ) can wake the CPU up. Before CPU enters IDLE Mode it should guerantee there will be no further AHB+ transaction. The nIRQ and nFIQ comes to the clock generation unit also to unmask hclk_cpu that enables the CPU to be woken-up and to recognize the interrupt consequently.
STOP Mode : The X-tal OSC is disabled to enter STOP Mode. The external interrupt may cause return to NORMAL Mode. When it entered STOP Mode the S5L9260X maintains statically it's latest state. The SDRAM(if exist) should be in self-refresh mode before entering STOP Mode. To support alarm function, Real Time Clock(RTC) also should be able to wake up S5L840F from STOP mode to NORMAL mode. STANDBY Mode : At this power saving mode, just RTC and X-tal for RTC is operating and all others are powered-down. We can't display TIME on the LCD because the CPU and the LCD interface unit will be powereddown at this mode. But the time is correctly maintained in the RTC and when woken up, the TIME can be displayed on the LCD. RTC operation with TIME display on an LCD requires RTC, CPU, BUSes and LCDIF to be alive, so this is the case of SLOW power saving mode. To enter STOP/Standby mode follow the sequence : 1. If pclk == hclk / 2, make pclk is equal to hclk 2. CalmADM3 sends the STOP/Standby power saving command to clock generation unit. The FSM in the clock generation unit excutes the following sequence (step 3~step6).
6-5
CLOCK & POWER MANAGEMENT
S5L840F (Preliminary Spec)
3. Masks all clocks. 4. Changes clock source to X-tal OSC from PLL. 5. Controls the PLL to be disabled (power-down). 6. Disable X-tal OSC.(STOP mode only) To recover to NORMAL Mode : ( Initiated by external interrupt coming.) 1. External interrupt received. 2. Upon receiving the external interrupt, The clock and reset generation unit asserts wresetn to "LOW" that makes the X-tal OSC to be enabled. 3. The clock and reset generation unit releases the wresetn to "HIGH" after 128 counts of the extint_cnt[6:0]. The wresetn is to reset the WDT(watch dog timer) and possibly released before the oscillator becomes stable. 4. The WDT counts the clock which is possibly unstable and sends the clock generation unit the wdt_send signal that indicates the oscillator has been stablized. All clocks are disbled until wdt_start is received . (except the clock for the WDT of cource which uses the clock hclk_pre that never be masked.) 5. The CPU enables the PLL. 6. The CPU waits until the PLL settles monitoring the Lock flag (?) of the PLL. 7. Changes the clock source to PLL from X-tal OSC. (The CPU changes it ?)
6-6
S5H5002 RISC MICROPROCESSOR (Preliminary Spec)
CLOCK & POWER MANAGEMENT
Global Power Management :
STANDBY
wresetn sys_resetn (POR)
CalmRISC32 sys instruction
SLOW
Clear pll_bypass Set pll_bypass
NORMAL
CalmRISC32 sys instruction wresetn
nFIQ or nIRQ
CalmRISC32 sys instruction
IDLE
STOP
Figure 6-5. The Global Power management
6-7
CLOCK & POWER MANAGEMENT
S5L840F (Preliminary Spec)
Local Power Management : While staying in NORMAL Mode the CPU can mask each of the clocks for AHB and APB peripheral devices to exploit power save as following : Besides the global power saving mode stated above, we provide local power management scheme so that the CPU can disable each peripheral device by masking the clock to the device when it is not needed to operate.
Classification No external events involved
Devices IIS UART IIC SPI SPDIF LCD I/F ADC RTC
Events
External events involved
USB MS I/F SMC I/F SD Card I/F MMC Card I/F
USB connection Card Insertion Card Insertion Card Insertion Card Insertion
6-8
S5H5002 RISC MICROPROCESSOR (Preliminary Spec)
CLOCK & POWER MANAGEMENT
1. RTC Power Issues
S5L840F does not provide a separate power and ground for RTC.
2. USB power management :
The USB don't have to operate when it's not connected to USB cable. Therefore the USB clocks can be masked after boot by CPU when it's not used..
According to USB standard USB device goes to Suspend state when there is no USB Bus activity during more than 2.5us. S5L840F USB Core sets D1 bit to "1" when it comes to Suspend state.
USB Power management Register
Name bit CPU (ClamRISC32) SUSPEND_MODE D1 R R/W This bit is set by the USB when it enters suspend mode UC_RESUME D2 R/W R The MCU sets this bit for a duration of 10ms to initiate a resume signaling USB_RESET D3 R Set The USB sets this bit if reset signaling is received from the host USB Core Description
When USB cable is disconnected or there is no USB signal detected USB goes to suspend state. The CPU should check D1 bit periodically to recognize that USB goes to suspend state. Then CPU controls to disable both of USB master clock and USB 48Mhz clock. During the USB is in it's Suspend state, when USB signal from host is detected USB core generates interrupt. This interrupt is generated even when there is no clock supplied to USB core. The CPU recognizes the USB connection by the interrupt, enables USB clocks and sets the bit D2 of the USB power management register to "1". Then the USB changes it's state to Resume state.
6-9
CLOCK & POWER MANAGEMENT
S5L840F (Preliminary Spec)
3. Memory Stick Interface and Smart Media Card Interface Power Management :
The Memory Stick Interface and Smart Media Card Interface Unit may be powered- down when they don't have cards in their slots. The following is a senario about how a card can be detected automatically in it's slot. This is based on guess!
When a card is inserted in it's slot the external circuitry (with a circuit inside the card) might give a dc voltage level which is different to the level shown when the card is disconnected. This signal might be connected to external interrupt pin (or GPIO ??) for CPU to recognize the card insertion.
The CPU may enable the clocks for Memory Stick Interface and Smart Media Card Interface each time when it needs to access the cards and disable the clocks after each access. The CPU might need to check the status of the card interface before disables the clock. (We need to check if there is any limitation on when the clock can be disabled safely to be woken-up and work properly later time.)
4. SD Card and Multi-Media Card Power Management :
THE CPU POLLS THE SC CARD INTERFACE TO IDENTIFY IF A CARD IS INSTALLED OR NOT. IF NOT INSTALLED IT MASKS THE CLOCK FOR THE SC CARD INTERFACE. WHEN THE CPU DOES NOT WANT TO ACCESS THE SC CARD IT MAY MASK THE CLOCK FOR THE SC CARD INTERFACE. (IS THIS CORRECT ??)
6-10
S5H5002 RISC MICROPROCESSOR (Preliminary Spec)
CLOCK & POWER MANAGEMENT
RESET CONTROLLER
The reset controller manages the various reset sources in the S5L840F. For a programmer, two reset control registers are provided: one used to invoke software reset and one to read the status showing why the processor is reset after the reset sequence. After booting from the reset, software can examine the reset status register (RSTSR) to determine which types of reset has caused the reset condition. Three types of reset in the S5L840F are described below: Hardware Reset Hardware reset is invoked when the nRESET pin is asserted, and all units in the S5H5002 are initialized to a known state. Hardware reset is intended to be used for power-up only. Because the memory controller receives a full reset, all dynamic memory(DRAM/SDRAM) contents will be lost during hardware reset. The nRESET_OUT pin is asserted during hardware reset. Software Reset Software reset is invoked when the software reset (SWR) bit in the SWRCON is set by software. After the SWR bit is set, the S5L840F stays in reset state for 128 APB bus clocks (PCLK) and then is allowed to boot again. The nRESET_OUT pin is asserted during software reset Watchdog Reset Watchdog reset is invoked when the watchdog enable bits in the WTCON[7:0] are set and the watchdog timer counter (WTCNT) overflows. The reset sequence of watchdog initiated reset is identical to software reset. When the WTCNT overflows, the S5L840F stays in reset state for 128 APB bus clocks (PCLK) and then is allowed to boot again. The nRESET_OUT pin is asserted during watchdog reset.
6-11
CLOCK & POWER MANAGEMENT
S5L840F (Preliminary Spec)
CLOCK AND POWER MANAGEMENT SPECIAL FUNCTION REGISTERS
PLL PMS VALUE REGISTER (PLLPMS) Fpllo = Fin * (m+1) / 2(s+1)
Table 6-3. Recommended Value of MDIV, SDIV M S Fvco [MHz] Fout [MHz]
5859 5859 5166 5166 5166 5511 5511 5511 5511 5512 5624 5624 5624 5999 5999 5999 5999 6201 6749
0 1 0 1 2 0 1 2 3 0 0 1 2 0 1 2 3 0 0
192.02048 192.02048 169.312256 169.312256 169.312256 180.617216 180.617216 180.617216 180.617216 180.649984 184.32 184.32 184.32 196.608 196.608 196.608 196.608 203.227136 221.184
96.01024 48.00512 84.656128 42.328064 21.164032 90.308608 45.154304 22.577152 11.288576 90.324992 92.16 46.08 23.04 98.304 49.152 24.576 12.288 101.613568 110.592
NOTE: This value may be calculated using PLLSET.EXE utility from Samsung. This PLL is not guaranteed that the PMS
6-12
S5H5002 RISC MICROPROCESSOR (Preliminary Spec)
CLOCK & POWER MANAGEMENT
values are all zeros.
6-13
CLOCK & POWER MANAGEMENT
S5L840F (Preliminary Spec)
CLOCK Control Register (CLKCON)
Register CLKCON
Address 0x3C50 0000
R/W R/W
Description Clock control Register
Reset Value 0x0000 0000
CLKCON UCLK_MASK RCLK_MASK MCLK_MASK PCLK_DIVON UCLK_DIVON MCLK_DIVON HCLK_SEL UCLK_SEL MCLK_SEL UCLK_DIV
Bit [31:27] [26] [25] [24] [23] [22] [21] [20] [19:18] [17:16] [15:14] [13:12] [11:8] [7:4] Reserved 0 = UCLK enable 0 = RCLK enable 0 = MCLK enable Reserved 0 = prescaler off 0 = prescaler off 0 = prescaler off Reserved 00 = OSC 10 = PLL1 00 = OSC 10 = PLL1 00 = OSC 10 = PLL1 Reserved 4-bit prescaler value
Description 1 = UCLK disable 1 = RCLK disable 1 = MCLK disable 1 = prescaler on 1 = prescaler on 1 = prescaler on 01 = PLL0 11 = Not Used 01 = PLL0 11 = Not Used 01 = PLL0 11 = Not Used
Initial State 0 0 0 0 0 0 0 0 00 00 00 00 0000 0000
UCLK = input clock / (UCLK_DIV + 1) when UCLK_DIVON == 1 MCLK_DIV [3:0] 4-bit prescaler value MCLK = input clock / (MCLK_DIV + 1) when MCLK_DIVON == 1 0000
6-14
S5L840F (Preliminary Spec)
CLOCK & POWER MANAGEMENT
PLL PMS VALUE REGISTER (PLLPMS) Register PLL0PMS PLL1PMS PLLPMS Reserved MDIV Reserved SDIV Address 0x3C50 0004 0x3C50 0008 Bit [31:30] [29:16] [15:2] [1:0] Reserved Main divider control Reserved Post-divider control Undefined Undefined R/W R/W R/W Description PLL PMS value Register PLL PMS value Register Description Reset Value Undefined Undefined Initial State
PLL LOCK COUNT REGISTER (PLLLCNT) Register PLL0LCNT PLL1LCNT PLLLCNT Reserved LOCK_CNT Address 0x3C50_0014 0x3C50_0018 Bit [31:13] [12:0] Reserved PLL lock count value (down counter) 0x1FFF R/W R/W R/W Description PLL0 lock count register PLL1 lock count register Description Reset Value 0x0000 1FFF 0x0000 1FFF Initial State
NOTE: Maximum PLL locking time = 150 us
PLL LOCK STATUS REGISTER (PLLLOCK) Register PLLLOCK PLLLOCK Reserved PLL1_LOCK PLL0_LOCK Address 0x3C50 0020 Bit [31:2] [1] [0] Reserved PLL1 Lock Status 0 : Progress PLL0 Lock Status 0 : Progress 1 : Locking done 1 : Locking done 0 0 R/W R Description PLL lock status register Description Reset Value 0 Initial State
6-15
CLOCK & POWER MANAGEMENT
S5L840F (Preliminary Spec)
PLL CONTROL REGISTER (PLLCON) Register PLLCON PLLCON Reserved PLL1_PWD PLL0_PWD Address 0x3C50 0024 Bit [31:2] [1] [0] Reserved PLL1 Power Down 0 : PLL1 is turned off. PLL0 Power Down 0 : PLL0 is turned off. 1 : PLL0 is turned on. 1 : PLL1 is turned on. 0 0 R/W R/W Description PLL control register Description Reset Value 0 Initial State
6-16
S5H5002 RISC MICROPROCESSOR (Preliminary Spec)
CLOCK & POWER MANAGEMENT
CLOCK POWER CONTROL REGISTER (PWRCON) Register PWRCON PWRCON CLK14 : GPIO CLK13 : TIMER CLK12 : ADC IF CLK11 : LCD IF CLK10 : RTC CLK9 : IIS CLK8 : SPDIF CLK7 : IIC CLK6 : SPI CLK5 : UART CLK4 : SDC/MMC CLK3 : Memory Stick CLK2 : SMC CLK1 : USB CLK0 : APBIF Address 0x3C50_0028 Bit [31:15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] Reserved 0 = Disable 0 = Disable 0 = Disable 0 = Disable 0 = Disable 0 = Disable 0 = Disable 0 = Disable 0 = Disable 0 = Disable 0 = Disable 0 = Disable 0 = Disable 0 = Disable 0 = Disable 1 = Enable 1 = Enable 1 = Enable 1 = Enable 1 = Enable 1 = Enable 1 = Enable 1 = Enable 1 = Enable 1 = Enable 1 = Enable 1 = Enable 1 = Enable 1 = Enable 1 = Enable R/W R/W Description Clock power control register Description Reset Value 0x0020 4000 Initial State 0000 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6-17
CLOCK & POWER MANAGEMENT
S5L840F (Preliminary Spec)
SOFTWARE RESET CONTROL REGISTER (SWRCON) The software reset control register has a software reset bit, which when set, causes a reset of the S5L840F. The software-reset bit (SWR) is located within the least significant bit of the write-only software reset register (SWRCON). Writing a one to this bit causes all on-chip resources to reset but does not cause the PLL to go out of lock. The software reset bit is self-clearing. It is automatically cleared to zero after a few system clock cycles once it is set. Writing zero to the software reset bit has no effect. Care should be taken to restrict access to this register by programming MMU permissions. The following table shows the SWRCON. Register SWRCON Address 0x3C50_0030 R/W W Description Software reset control register Reset Value 0x0000 0000
SWRCON SWR
Bit [7:0] Software reset.
Description 1010_0101 = Invoke a software reset of the chip. Other value = Do not invoke a software reset of the chip. This bit is self-clearing, and is automatically cleared several system clock cycles after it has been set.
Initial State 0
6-18
S5H5002 RISC MICROPROCESSOR (Preliminary Spec)
CLOCK & POWER MANAGEMENT
RESET STATUS REGISTER (RSTSR) To determine the last cause or causes of the reset, the CPU can refer to the reset status register (RSTSR). The S5L840F has three sources of reset: * * * Hardware reset Software reset Watchdog reset
Each RSTSR status bit is set by a different source of reset, and can be cleared by setting a one of the other reset status bits. Note that the hardware reset state of software and watchdog reset bit is zero. The table below shows the status bits within RSTSR. Register RSTSR Address 0x3C50_0034 R/W R/W Description Reset status register Reset Value 0x0000 0001
RSTSR WDR
Bit [2] Watchdog reset.(Read only)
Description 0 = Watchdog reset has not occurred. 1 = Watchdog reset has occurred This bit is cleared automatically when one of the other reset status bit is set.
Initial State 0
SWR
[1]
Software reset.(Read only) 0 = Software reset has not occurred. 1 = Software reset has occurred This bit is cleared automatically when one of the other reset status bit is set.
0
HWR
[0]
Hardware reset.(Read only) 0 = Hardware reset has not occurred. 1 = Hardware reset has occurred This bit is cleared automatically when one of the other reset status bit is set.
1
6-19
CALMADM
FUNCTIONAL SPEC
CalmADM3-0.2-030715
CalmADM3
CalmRISC16 and CalmMAC24 Based Audio DSP Module with Host Capability
Functional Specification 1.0 Ver-030715
JoongEon Lee, Optical Player P/J
40-1
FUNCTIONAL SPEC
CALMADM
REVISION HISTORY
Verion 0.0 0.1 Engineer J.E.Lee J.E.Lee Date 2003-05-31 2003-06-11 Description First version. Copied & modified from CalmADM2_spec_v01. Major changes from the last version: - added nFIQ input pin - changed fast interrupt generation mechanism - added chapter 5, "Information for CalmShine Development" Major changes from the last version: - added SYS_IDLE command - included BIST modules - added RIACE flag in FIECFG of HFRS - added DBU output ports - fixed some errata Green colored characters denote changes.
1.0
J.E.Lee
2003-07-15
40-2
CALMADM
FUNCTIONAL SPEC
TABLE OF CONTENTS
1 Product Overview 2 CalmADM3 Programming Model 2-1 memory configuration 2-1-1 Program Memory 2-1-2 Data Memory 2-1-3 MEMORY REGIONS 2-1-4 MAC AREA CONSIDERATIONS 2-2 Sequential Data Access 2-2-1 CONCEPTS AND DEFINITIONS 2-2-2 OPERATIONS in linear mode 2-2-3 OPERATIONS in ring mode 2-3 SFRS Interface 2-4 CalmADM3 Internal Controls 2-4-1 CalmADM3 Fast Interrupt 2-4-2 CalmADM3 SYS commands 2-5 CalmADM3 Host Function Register Set 3 CalmADM3 Hardware Specifications 3-1 Interface Spec. 3-1-1 pin descriptions 3-1-2 pin timing diagrams 3-2 Arbiter 3-3 AHBMIU (AHB Master Interface Unit) 3-4 INSTRUCTION CACHE 3-5 DATA CACHES 3-5-1 X-Cache 3-5-2 X/Y-Cache as calm area data cache 3-6 SBFU (S-buffer unit) 3-7 SFRSI (SFRS interface unit) 4 Constraints on using CalmADM3 4-1 Constraints on using CalmRISC16F 4-2 Constraints on using CalmMAC24F 4-3 Constraints on accessing sequential buffers 4-4 Constraints on accessing X/Y-Caches 4-5 Definitions of Abbreviations 5 Information for CalmShine Development 5-1 Simulator Spec. 5-2 Emulator Spec.
40-3
FUNCTIONAL SPEC
CALMADM
1
Product Overview
INTRODUCTION
CalmADM3, a CalmRISC16 and CalmMAC24 based audio DSP module with host capability, is designed for highquality audio processing and micro system control. It includes Samsung's 16-bit MCU, CalmRISC16, and 24-bit DSP, CalmMAC24. CalmADM3 also includes three caches, one instruction cache and two data caches. To keep high performance with optimal die area, two data caches are adopted instead of large on-chip data memories typically used in other audio processors. Since it is used to encode/decode large audio data frames, CalmADM3 includes two sequential buffers to handle input/output data efficiently. These sequential buffers can be act as a kind of ring buffer also. Since CalmADM3 is based on a 16-bit MCU, CalmRISC16, but its target system bus, AMBA, is a 32-bit bus, CalmADM3 cannot access slave registers on the system bus in usual way. In CalmADM3, a specially designed slave register interface unit handles the 16-bit/32-bit data width conversion. In this document, we call CalmADM3 as an abbreviation, ADM.
Features
CalmRISC16F 16-bit low power & high performance RISC micro-controller Harvard style architecture: 4M byte program memory space, 4M byte data memory space 5-stage pipelined instruction execution 16-bit (half-word) instruction set Sixteen 16-bit general-purpose registers with eight 6-bit extension registers `F' denotes full scan version of CalmRISC16 In this document, we call CalmRISC16F as an abbreviation, Calm.
CalmMAC24F 24-bit (audword) high performance fixed-point DSP coprocessor for CalmRISC16 micro-controller 1 cycle 24x24 MAC operation 32K audword X data memory space & 32K audword Y data memory space 2 multiplier accumulator registers, 4 general accumulator registers, and 8 pointer registers `F' denotes full scan version of CalmMAC24 In this document, we call CalmMAC24F as an abbreviation, Mac.
*NOTE: WE DEFINED 24-BIT DATA UNIT OF CALMMAC24F AS aud-word IN THIS DOCUMENT.
40-4
CALMADM
FUNCTIONAL SPEC
System interface
SFRSI
CalmRISC16F IC
SFRS
XC
Scan interface
Arbiter & AHBMI
Bist interface
CalmMAC24F
AHB+ interface
YC
On/off-chip memories
Debug interface
SBF0 DBU SBF1 AHB+
Figure 1-1. CalmADM3 Block Diagram INTERNAL MEMORY Instruction cache: 256 bit line, 4K byte, direct-mapped cache X Data cache: 192 bit line, 6K byte, 2 way set associative cache Y Data cache: 192 bit line, 6K byte, 2 way set associative cache Two 16-byte sequential buffers: configurable sequential ring buffer mode or sequential linear buffer mode
AHB+ INTERFACE CalmADM3 acts as an AHB+ master to access on/off-chip memories including memory mapped slave registers.
SFRS INTERFACE Converts 16-bit dual-access from Calm to 32-bit bus access one-entry cache with auto-invalidation and auto-backup
Clock One AHB+ clock input
PERFORMANCE
40-5
FUNCTIONAL SPEC
CALMADM
Max. operating Frequency = 100MHz @ (Voltage: 1.65V - 1.95V, Temperature: -40 C ~ 125 C, Process: Samsung L18
2
2-1
CalmADM3 Programming Model
memory configuration
Calm View
4M byte Program Memory
(22 bit byte address)
System View
4G byte memory space
(32 bit byte address)
3FFFFFh 512K byte P7 region 380000h P7SIZE P7BASE
. . .
180000h 512K byte P2 region 100000h 512K byte P1 region 080000h 512K byte P0 region 000000h P0SIZE P0BASE P1SIZE P1BASE P2SIZE P2BASE
Figure 2-1. Program Memory Configuration
40-6
CALMADM
FUNCTIONAL SPEC
2-1-1 Program Memory
Program memory configuration is shown in Figure 2-1. 4M-byte cacheable instruction memory space is divided into 8 regions. Calm accesses these regions through an instruction cache, I-Cache. Each region is individually mapped to 4G-byte system memory space as defined by its BASE and SIZE fields of its configuration register in HFRS. For example, if [20:18] bits of PA, the 21-bit program address bus from Calm, equals "000b", it is in P0 region in Calm view. PA[17:0] is converted as a byte address (multiplied by 2), added with P0BASE and mapped to 32-bit system memory space. Before this address mapping, PA[17:0] is checked whether it is addressing the location beyond size limit defined by P0SIZE.
2-1-2 Data Memory
Data memory configuration is shown in Figure 2-2. 4M-byte data memory space is divided into 8 memory regions and 2 register areas. Each region is individually mapped to 4G-byte system memory space as defined by its BASE and SIZE fields of its configuration register in HFRS. Calm Regions Lower 2M-byte area of 4M-byte data memory space is divided into 4 regions, accessed by Calm only. Calm accesses these regions through two data caches (X-Cache and Y-Cache). As the cache for Calm regions,
Calm View
3FFFFFh 300000h 256K byte HFRS area 2C0000h 280000h 240000h 128K byte MAC Y area 220000h 128K byte MAC X area 200000h 180000h 100000h 80000h 000000h 256K byte SBL1 area 256K byte SBL0 area
System View
4G-byte memory space
(32-bit byte address)
4M-byte Data Memory
1M byte SFRS area
128M byte SFRS area SFRSBASE
MAC View
Two 32K-audword Data Memory unused unused YE YL XE XL
S1SIZE S1BASE S0SIZE S0BASE
unused YH unused XH
YE
YH
YL
4:3 data packing packed data
YSIZE*0.75 YBASE
unused unused
YE
YH
YL
4:3 data packing
packed data
XSIZE*0.75 XBASE C3SIZE C3BASE C2SIZE C2BASE C1SIZE C1BASE C0SIZE C0BASE
512K byte Calm3 region 512K byte Calm2 region 512K byte Calm1 region 512K byte Calm0 region 16bit
32bit
Figure 2-2. Data Memory Configuration
40-7
FUNCTIONAL SPEC
CALMADM
these two data caches operate similar to a two way set associative cache. If [21:19] bits of DA, the 22-bit data address bus from Calm, equals "000b", it is in C0 region in Calm view. DA[18:0] is added with C0BASE and mapped to 32-bit system memory space. Before this address mapping DA[18:0] is checked whether it is addressing the location beyond size limit defined by C0SIZE. MAC Regions MAC X and MAC Y are dual memory for dual load capability of Mac. Each is 32K-audword. Both of Calm and Mac can access these two regions. When DA[21:17] equals "10000b", Calm accesses X region. To access this region, Calm uses X-Cache as data cache. DA[16:0] from Calm is converted as X region address before get into X-Cache. When DA[21:17] is 10001b, Calm accesses Y region. To access this region, Calm uses Y-Cache as data cache. DA[16:0] from Calm is converted as Y region address before get into Y-Cache. Mac accesses two MAC areas with its two 15-bit audword data addresses, XA and YA. XA and YA are 2-bit left shifted (conversion to byte address) before get into the caches. The 6K-byte X-Cache covers 32K-audword MAC X region. The 6K-byte Y-Cache covers 32K-audword MAC Y region. The addresses from X-Cache and Y-Cache are converted as 4:3 reduction, added with XBASE/YBASE and mapped to 32-bit system memory space. Before this address mapping the addresses are checked whether they are addressing the location beyond size limit defined by XSIZE/YSIZE. Two words in highest address of MAC X and two words in highest address of MAC Y are reserved for accessing sequential block areas. SBL0/SBL1 REGIONS Sequential block regions are used mainly for input and output of audio stream data frames. Calm can access these regions randomly but Mac can access them in sequential way only. Since these regions are out of Mac's memory space, Mac cannot access these randomly. In ADM, a special logic was added so that Mac can access these regions sequentially. When DA[21:18] is 1001b, Calm accesses SBL0 area. DA[17:0] is added with S0BASE and mapped to 32-bit system memory address. Before this address mapping DA[17:0] is checked whether it is addressing the location beyond size limit defined by S0SIZE. When DA[21:18] is 1010b, Calm accesses SBL1 area similarly to SBL0 area. Since ADM has no caches for these areas, Calm accesses system memory directly when it accesses these areas. When XA or YA are 7FFEh, Mac accesses SBL0 area sequentially. When XA or YA are 7FFFh, Mac accesses SBL1 area sequentially. The sequential accesses are modulated with the size limit. Therefore, sequential accesses do not cause the size limit violation. More of sequential data accessing is described in later of this document. HFRS AREA HFRS (Host Function Register Set) area is reserved for memory-mapped registers of ADM. HFRS area resides 2C0000h to 2FFFFFh address space in Calm's data memory space. Registers in HFRS can be accessed by ADM only. Outside of ADM cannot access these. SFRS Areas SFRS (Special Function Register Set) area is reserved for system level memory-mapped registers. SFRS area is divided into two areas, PSFRS area for slave registers in APB IPs and HSFRS area for slave registers in AHB IPs. PSFRS area resides 380000h to 3FFFFFh address space in Calm's data memory space. 512K-byte PSFRS area is divided into 64 8K-byte blocks and mapped to 64M-byte system memory space. ADM can handle up to 64 APB
40-8
CALMADM
1M byte Logical SRFS Area 128M byte Physical SFRS Area 4G byte memory space
3FFFFFh 8K byte PSFRS 512K byte . . . 8K byte 380000h HSFRS 512K byte 8K byte 16K byte . . . 16K byte 300000h 16K byte 32 64
FUNCTIONAL SPEC
8K byte
. . . SFRS (APB) 64M byte
8K byte Address translation (simple stuffing)
1M
8K byte
PSFRSBASE
16K byte
. . . SFRS (AHB) 64M byte
16K byte
2M
16K byte
HSFRSBASE
Figure 2-3. SFRS Memory Map
SFRS(APB) case Calm Address
[21:19] = 111 [18:13] [12:0]
SFRS(AHB) case
[21:19] = 110 [18:14] [13:0]
Physical Address
[31:26] = PSFRSBASE
[25:20]
[19:13] =0
[12:0]
[31:26] = HSFRSBASE
[25:21]
[20:14] =0
[13:0]
Base concatenation
Zero stuffing
Figure 2-4. SFRS Address Translation IPs that have up to 8K-byte slave register set. HSFRS area resides 300000h to 37FFFFh address space in Calm's data memory space. 512K-byte HSFRS area is divided into 32 16K-byte blocks and mapped to 64M-byte system memory space. ADM can handle up to 32 AHB IPs that have up to 16K-byte slave register set. Memory map and address translation of SFRS are shown in Fig.2-3 and Fig.2-4.
2-1-3 MEMORY REGIONS
In ADM are 16 memory regions. The regions are assigned as Fig.2-5. Each region has corresponding region control registers and flag in HFRS. The region control is performed by hardware in ADM based on a region enable flag of RECFG register and base address field and region size field of region configuration register in HFRS. Because the base address field is 24-bit corresponding to [31:8] bit location of 32-bit physical memory address, each region can be aligned 256-byte step boundaries in physical memory
40-9
FUNCTIONAL SPEC
R15 R14 R13 R12 R11:R8 S1 S0 Y X C3:C0 R7:R0 P7:P0
CALMADM
Figure 2-5. Region Assignment
Size SIZE Code R0~R11 1KB 2KB 4KB 8KB 16KB 32KB 64KB 128KB 256KB 512KB 512KB R12,R13 (X,Y) logical 1KB 2KB 4KB 8KB 16KB 32KB 64KB 128KB 128KB 128KB 128KB physical 0.75KB 1.5KB 3KB 6KB 12KB 24KB 48KB 96KB 96KB 96KB 96KB R14,R15 (S0,S1) 1KB 2KB 4KB 8KB 16KB 32KB 64KB 128KB 256KB 256KB 256KB
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 others
Figure 2-6. Region Size Definitions map. The SIZE fields are defined as Fig.2-6. When Calm or Mac issues a memory access, ADM checks if the accessed region is enabled and if the accessed location is in valid region area defined by SIZE field. If one of these two checks results false, ADM issues an exception to Calm instead of issuing the physical memory access. Before ADM issues the physical memory access, it performs an address translation by adding BASE field to the logical address issued from processors.
2-1-4 MAC AREA CONSIDERATIONS
*NOTE: THIS SECTION IS EXACTLY SAME AS THE ONE IN CALMADM2 SPECIFICATION. IF YOU ARE FAMILIAR WITH CALMADM2, YOU DON'T NEED TO READ THIS SECTION.
The target Host of ADM is 32-bit machine, Mac is a 24-bit DSP and Calm is a 16-bit RISC processor. Because of different size of unit data among three processors, following two address conversions are needed for MAC X/Y areas. DA conversion for MAC Area Because of the data unit difference, Calm and Mac have different address maps of MAC X/Y area. (Look at the structure difference of MAC X/Y area between Calm View and Mac View in Figure2-2) Because of the difference, proper address conversion is needed when Calm accesses MAC X/Y area. DA[21:0] from Calm is converted to DA_mem[21:0] in following manner before it goes to caches or system memory. *DA to DA_mem conversion: if ((DA[21:17] == 0b10000) or (DA[21:17] == 0b10001)) DA_mem[21:0] = "DA[21:17],DA[15:1],~DA[16],DA[0]"
40-10
CALMADM
FUNCTIONAL SPEC
Else DA_mem[21:0] = DA[21:0]
4:3 Reduction for Unused Bytes Since Mac is a 24-bit DSP and its memory data are word (32-bit) aligned, there are not-used bytes in data words of MAC X/Y area. Since there is no physical memory for these bytes, two things should be considered. The one is accessing these bytes by Calm. Calm may access these not-used bytes, but a write to these bytes cannot be done and a read from these bytes always results 00h. The second is waste of system memory area. If MAC X/Y areas are mapped to system memory directly, it causes waste 1/4 of system memory area. Therefore, in ADM, addresses of MAC X/Y area from X/Y-caches are converted as 4:3 reduction before mapped to system memory addresses. As a result of this conversion, size of each MAC X area and MAC Y area will be 96K-bytes in system memory instead of 128K-bytes.
2-2
Sequential Data Access
*NOTE: THIS SECTION IS EXACTLY SAME AS THE ONE IN CALMADM2 SPECIFICATION. IF YOU ARE FAMILIAR WITH CALMADM2, YOU DON'T NEED TO READ THIS SECTION.
If a data block in the system memory is well-aligned and well-known stream data, it can be accessed in sequential. In ADM, user can define two sequential blocks in Calm data memory area and can access them sequentially through sequential buffers. There are two sequential access modes, linear mode and ring mode.
4M byte Data Memory
240000h
SBL0OFF SBF0
0 1 2 3
SBL0 area SBL0
280000h
CalmMAC24F
SBF1
0 1 2 3
SBL1OFF
SBL1 area SBL1
Figure 2-6. Sequential Access Data Flow
40-11
FUNCTIONAL SPEC
CALMADM
2-2-1 CONCEPTS AND DEFINITIONS
Sequential Block Areas Data memory area in which sequential blocks can be defined. In Calm data memory area, two 256K-byte sequential block areas are defined. One starts from 240000h address and the other starts from 280000h. Calm can access these areas randomly but Mac can't access in normal way because these areas are defined out of MAC X/Y areas. ADM offers special way for Mac to access these areas sequentially.
Sequential Blocks Well-aligned data memory area that can be sequentially accessed by Mac through sequential buffers. Unit data in a sequential block can be word or half-word. However, a sequential block should be word aligned for efficient system memory access. Data in a sequential block are addressed with offset register. These blocks are dynamic blocks that can be created, used and removed by software. In linear mode, the size and boundary of a sequential block are implicitly defined by how user program accesses the sequential block. In ring mode, the size and boundary of a sequential block are explicitly defined by the values of begin offset register and end offset register.
Sequential Buffers A kind of FIFO that is used as buffer memory for Mac to access sequential blocks sequentially. These buffers can be both read buffer and write buffer. Pre-loading and post-storing capability are supported. These capabilities can be done explicitly by giving special command into control registers. Size of sequential buffers 128-bits 4 data for word data, 8 data for half-word data Address of sequential buffers sequential buffers are defined as a memory data located in special address. SBF0 : 21FFF8h (in X area) or 23FFF8h (in Y area) SBF1 : 21FFFCh (in X area) or 23FFFCh (in Y area) Sequential Block Offset Registers 18-bit registers that contain offset address of memory data to be accessed at next sequential access.
40-12
CALMADM
FUNCTIONAL SPEC
-
Offset registers are automatically increased just after a sequential access. In ring mode, incremented offset register is compared with the end offset register. If two register values are same, an offset register is set as the value of the begin offset register. Offset registers can be read or written directly since these are memory mapped in I/O area of Calm. When offset register is written, the value can be any address in sequential block area. The written value is independent from the values of the boundary-offset registers even in ring mode. The bases of offsets are start addresses of sequential block areas. The offset values are byte-address.
Sequential Block Boundary Offset Registers 18-bit registers that contain boundary offset values (begin/end) of a sequential block used in ring mode. In ring mode, a sequential block is define as below: begin offset =< SBL < end offset CAUTION: end offset is not included in sequential block. In linear mode, boundary offsets are not used. These registers can be read or written directly since these are memory mapped in I/O area of Calm. The bases of boundary offsets are start addresses of sequential block areas. The boundary-offset values are byte-address.
Ring mode vs. linear mode In linear mode, the size and boundary of a sequential block is not fixed. Defining a sequential block and checking its boundary totally depend on user program. In ring mode, the size and boundary of a sequential block is defined by the values of begin offset register and end offset register. Boundary checking is performed by hardware. In ring mode, when the offset register is increase to meet the value of end offset register, two operations are automatically performed by hardware. 1. offset wrapping The offset register is set as the value of begin offset register. (we call it `wrapping' in this document) 2. interrupt Corresponding interrupt flag is set and interrupt is forced to Calm if the interrupt is enabled.
2-2-2 OPERATIONS in linear mode
Following tables show how to access SBL0 in linear mode. SBL1 can be accessed similarly.
40-13
FUNCTIONAL SPEC
CALMADM
Table 2-1. SBL0 AS A SEQUENTIAL READ BLOCK IN LINEAR MODE Explicit Operations Set SBL0OFF Run buffer fill command Implicit Operations - Set SBL0OFF as start offset of sequential block - Invalidate all data words in SBF0 - Fetch words located from {SBL0OFF[17:4],SBL0OFF[3:2],00} to {SBL0OFF[17:4],11,00} in SBL0 into SBF0 - Validate fetched words in SBF0 - Data read - Invalidate read word and Increase SBL0OFF - If SBF0 is empty - fetch new 4 words in (SBL0OFF[17:4],0000b) location of SBL0
Read SBF0
Repeating read from SBF0 results sequential reads
Table 2-2. SBL0 AS A SEQUENTIAL WRITE BLOCK IN LINEAR MODE Explicit Operations Set SBL0OFF Write to SBF0 Implicit Operations - Set SBL0OFF as start offset of sequential block - Invalidate all data words in SBF0 - Data write - Validate written word and Increase SBL0OFF - If SBF0 is full - flush valid words in SBF0 into (SBL0OFF[17:4]-1,0000b) location of SBL0 and invalidate flushed words.
Repeating write into SBF0 results sequential writes Run buffer flush command Flush valid words and invalidate flushed words
Table 2-3. SBL0 area as randomly accessed data memory Explicit Operations Calm accesses SBL0 area in system memory directly To keep data consistency, - ADM checks if it is hit on one-lined-cache (SCACHE0) (SCACHE0 consists of SBL0OFF as tag and SBF0 as a data line.) - write policy: write-through - No replacement is done on miss Implicit Operations
2-2-3 OPERATIONS in ring mode
Following tables show how to access SBL0 in ring mode. SBL1 can be accessed similarly.
40-14
CALMADM
FUNCTIONAL SPEC
Table 2-4. SBL0 AS A SEQUENTIAL READ BLOCK IN RING MODE Explicit Operations Set SBL0BEGIN and SBL0END Set SBL0OFF Run buffer fill command Read SBF0 - Data read - Invalidate read word and Increase SBL0OFF - If SBL0OFF is equal to SBL0END, - set SBF0 interrupt flag - invalidate entire SBF0 - set SBL0OFF as SBL0BEGIN - Fetch words located from {SBL0OFF[17:4],SBL0OFF[3:2],00} to {SBL0OFF[17:4],11,00} in SBL0 into SBF0 - Validate fetched words in SBF0 - If SBF0 is empty - fetch new 4 words from (SBL0OFF[17:4],0000b) location of SBL0 * no special implicit operations * same as descriptions in table2-1 Implicit Operations
Repeating read from SBF0 results sequential reads in ring mode
Table 2-5. SBL0 AS A SEQUENTIAL WRITE BLOCK IN RING MODE Explicit Operations Set SBL0BEGIN and SBL0END Set SBL0OFF Write to SBF0 * no special implicit operations * same as descriptions in table2-2 - Data write - Validate written word and Increase SBL0OFF - If SBL0OFF is equal to SBL0END, - set SBF0 interrupt flag - Flush valid words and invalidate flushed words - set SBL0OFF as SBL0BEGIN - If SBF0 is full - flush valid words in SBF0 into (SBL0OFF[17:4]-1,0000b) location of SBL0 and invalidate flushed words. Implicit Operations
Repeating write into SBF0 results sequential writes Run buffer flush command * same as descriptions in table2-2
In ring mode, Calm randomly accesses SBL0 area in the same way as the case of linear mode. Refer table2-3.
40-15
FUNCTIONAL SPEC
CALMADM
16-bit read miss
Read Valid
16-bit write
16-bit read hit
First Read Recover SFRBUF
Pop SFRBUF
recover command
Second Read
SFRBUF Calm
SFRS SFRS
Calm SFRBUF
16-bit read
Stand-By
16-bit write exception
Backup SFRBUF
Push SFRBUF
Second Write
SFRBUF Calm SFRS SFRS
16-bit write hit 16-bit read
First Write
Calm SFRBUF
Write Valid
16-bit write miss
Notes - 8-bit write no operation - 8-bit read dummy read, fixed to reading zero - After Backup Stand-By state - After Recover recovered state according to the recovered state flags
Figure 2-7. SFRSI State & Function Diagram
2-3
SFRS Interface
Since ADM works as a host processor of 32-bit AMBA bus based system, ADM should read and write 32-bit SFRS registers in the IPs on the 32-bit AMBA buses. Because ADM is based on a 16-bit MCU, CalmRISC16, it cannot access SFRS registers in usual way. In ADM, a specially designed slave register interface unit, SFRSI, handles the 16-bit/32-bit data width conversion. To access a 32-bit register, Calm accesses the register twice. One is for higher half of the register. the other is for lower half of the register. We call this accessing twice as dual-access (dual-read, dual-write). Main function of SFRSI is conversion of dual-access from Calm to one 32-bit access to AMBA bus. To perform this conversion, SFRSI is designed as an one-entry cache composed with a 16-bit data register, an address register tagged to the data, a valid flag and a read/write mode flag. In addition to the one-entry cache function, SFRSI performs two special functions. One is auto-invalidation on hit. It guarantees that ADM converts two 16-bit Calm accesses to one 32-bit bus access. Without this auto-invalidation, 3 or more Calm accesses may cause only 1 bus access when Calm repeats accessing same SFRS register. The other one is auto-backup on exception. Since dual-access is a single access to a SFRS register, it is an atomic operation. However, an exception (interrupt) may occur during Calm performs a dual-access. It may separate an atomic operation into two operations and may cause a failure on system operation. To prevent the separation of atomic dual-access, the contents of one-entry cache in SFRSI should be backup on exception so that they can be recovered before returning from the exception handling routine. In ADM, the backup on exception is done automatically by SFRSI hardware and the recovery is done on special command. We defined one of SYS commands of Calm as the recovery command so that the system programmers can insert the command into the end of exception handling routines. Fig.2-7 shows the operation of SFRSI. When reading a SFRS register, dual-read is not mandatory. Calm can read any SFRS register freely in 16-bit mode. When writing, dual-write is mandatory. Calm can write any SFRS register in 16-bit mode, but only when the write hit occurs, the SFRS register is physically written. The SFR buffer data written by Calm is written to the
40-16
CALMADM
FUNCTIONAL SPEC
SFRS register if next SFRS access results write hit. The data is discarded if the next SFRS access is read or write-miss.
2-4
CalmADM3 Internal Controls
2-4-1 CalmADM3 Fast Interrupt
ADM has two fast interrupt signals. One is nFIQ, one of ADM input pins. The other is internal fast interrupt signal. When one or two of these are active, fast interrupt request is issued to Calm. INTERNAL FIQS In ADM are four sources of internal fast interrupt. These sources are defined as interrupt pending flags of ADMSTAT register in HFRS. Two of them, S0WIF and S1WIF, are wrapping interrupt flags set by sequential buffer unit described in section 2-2-1. Remaining two of them, PRIAIF and DRIAIF, are results of region check described in section 2-1-3. When one or more of 8 program region checks failed, PRIAIF is set. When one or more of 8 data region checks failed, DRIAIF is set. User can enable/disable each interrupt source by set/resetting corresponding interrupt enable flag of FIQCFG in HFRS. If one or more among enabled interrupt pending flags are set, the internal fast interrupt signal is active. User should clear the interrupt pending flag by writing 1 into that flag before returning from the corresponding interrupt service routine.
2-4-2 CalmADM3 SYS commands
In ADM, two SYS commands are used internally. SYS #5h is defined as `sys_idle' meaning that Calm goes to idle mode after execution of this command. Note that, before `sys_idle' is issued, `ready_clk_down' flag in ADMSTAT register should checked if it's on. Upon the interrupts or wake up command from debugger unit, Calm exits from idle mode. SYS #18h is defined as `sys_rsfrb' meaning recovery of SFR buffer described in section 2-3.
2-5
Address Base
CalmADM3 Host Function Register Set
The address values below are 7bit off set values. The full address values are additions of the offsets and the base address.
40-17
FUNCTIONAL SPEC
CALMADM
Base address of ADM function register set: 2C0000h
Register Set 1: CONFIG ADMCFG: ADM configuration register BASE + 0h Bit 15 Name SBF0 mode [3] Mode : read/write Description Sequential access mode selection bit 0 : linear mode 1 : ring mode * when SBF0 mode [2] is 0, access unit of external memory is 32 bit. * when SBF0 mode [2] is 1, access unit of external memory is 16 bit. 00x : mac input[23:0] <-- external input[23:0] 01x : mac input[23:0] <-- external input[32:8] 100 : mac input[23:0] <-- zero extension of external input[15:0] 101 : mac input[23:0] <-- sign extension of external input[15:0] 11x : mac input[23:8] <-- external input[15:0], mac input[7:0] <-- 00h 000 : external output[31:0] <-- zero extension of mac output[23:0] 001 : external output[31:0] <-- sign extension of mac output[23:0] 01x : external output[31:8] <-- mac output[23:0], external output[7:0] <-- 00h 10x : external output[15:0] <-- mac_output[15:0] 11x : external output[15:0] <-- mac_output[23:8] 11:8 7:6 SBF1 mode [3:0] * Similar to the description of `SBF0 mode [3:0]' not used (reading returns zero) XY-Cache round robin code. When a Calm area access is cache-missed, one of X- or Y-Cache is replaced according to this code. 5:4 xyrr 00: X- and Y-Cache are selected one after another (round robin). At the first miss, X-Cache is selected. 01: X-Cache is selected. 1x: Y-Cache is selected. not used (reading returns zero) This flag is for partial invalidation. If it is set, all LDC instruction of Calm invalidates the target address line in I-Cache. reset value : 0000h
14:12
SBF0 mode [2:0]
3:1 0
ldcinv
* Note: When sbf0mode/sbf1mode flags are written, newly updated values are not effective to the operation of sequential buffers. New values are effective after the sequential buffer is newly initialized, which means that SBL0OFF/SBL1OFF registers are newly written. * Note: xyrr bits should change while both X- and Y-Caches are disabled. Otherwise, data coherence may corrupt.
40-18
CALMADM
FUNCTIONAL SPEC
FIECFG: Fast Interrupt Enable/disable configuration register BASE + 2h Bit 15:9 8 7:4 3 Name RIACE DRIAIE Mode : read/write Description not used (reading returns zero) Region Invalid Access Check Enable 0 : region check disable, 1 : region check enable not used (reading returns zero) Data Region Invalid Access Interrupt Enable 0 : interrupt disable, 1 : interrupt enable Program Region Invalid Access Interrupt Enable 0 : interrupt disable, 1 : interrupt enable Sequential Buffer 1 Wrapping Interrupt Enable 0 : interrupt disable, 1 : interrupt enable Sequential Buffer 0 Wrapping Interrupt Enable 0 : interrupt disable, 1 : interrupt enable
reset value : 0000h
2
PRIAIE
1
S1WIE
0
S0WIE
* Note: Enabling `region invalid access check' may cause performance degradation of ADM in terms of both speed and power. You can set RIACE flag only in debug mode, and reset it in normal operation mode that needs the full performance of ADM.
RECFG: Region Enable/disable configuration register BASE + 4h Bit 15:0 Name RE Mode : read/write Description 0 : region disable, 1 : region enable
reset value : 0001h
* Note: RE[0] is reset as high (enabled) because Region0 contains boot code(reset vector).
R0CFG_H/L: Region0 Base & Size configuration register BASE + 6h Bit Name Mode : read/write Description
reset value : 0000h_0002h
40-19
FUNCTIONAL SPEC
CALMADM
[15:0]
BASE[23:8]
Base address of Region0 in physical memory space. Mapped to [31:16] of physical memory address.
BASE + 8h Bit [15:8] [7:4] Name BASE[7:0] -
Mode : read/write Description Base address of Region0 in physical memory space. Mapped to [15:8] of physical memory address. not used (reading returns zero) Size code of Region 0. 0000: 1K-byte 0001: 2K-byte 0010: 4K-byte 0011: 8K-byte 0100: 16K-byte 0101: 32K-byte 0110: 64K-byte 0111: 128K-byte 1000: 256K-byte 1001: 512K-byte others: 512K-byte
[3:0]
SIZE
R1CFG_H/L ~ R15CFG_H/L: Region1~15 Base & Size configuration register BASE + Ah, Eh, ..., 42h Bit [15:0] Name BASE[23:8] Mode : read/write Description
reset value: xxxx_xxxxh
Base address of Region1~15 in physical memory space. Mapped to [31:16] of physical memory address.
BASE + Ch, 12h, ..., 44h Bit [15:8] [7:4] [3:0] Name BASE[7:0] SIZE
Mode : read/write Description Base address of Region1~15 in physical memory space. Mapped to [15:8] of physical memory address. not used (reading returns zero) Size code of Region 0. *code definition is same as SIZE definition of R0CFG
40-20
CALMADM
FUNCTIONAL SPEC
SFRSCFG: SFRS Area Base configuration register BASE + 46h Bit [15:10] [9:8] [7:2] [1:0] Name PSFRSBASE HSFRSBASE Mode : read/write Description
reset value : xxxxh
Base address of SFRS(APB) area in physical memory space. Mapped to [31:26] of physical memory address. not used (reading returns zero) Base address of SFRS(AHB) area in physical memory space. Mapped to [31:26] of physical memory address. not used (reading returns zero)
Register Set 2: CONTROL registers CACHECON: Cache control register BASE + 48h Bit [15:10] Name Mode : write only. Reading returns zero. Description not used (reading returns zero) 00: No operation 01: I-Cache invalidation 10: I-Cache enable. 11: I-Cache disable (go to bypass mode). not used (reading returns zero) 000: No operation 001: X-Cache invalidation 010: X-Cache enable. 011: X-Cache disable (go to bypass mode). 1xx: X-Cache flush not used (reading returns zero) * Similar to the description of `xc command flag' reset value : 0333h
[9:8]
ic command flag
[7]
-
[6:4]
xc command flag
[3] [2:0]
yc command flag
SBFCON: Sequential buffer control register BASE + 4Ah Bit [15:14] Name Mode : write only. Reading returns zero. Description not used (reading returns zero)
reset value : 0000h
40-21
FUNCTIONAL SPEC
CALMADM
[13:12] [11:10] [9:8] [7:0]
sbf0 command flag sbf1 command flag -
00,11: No operation 01: buffer fill command 10: buffer flush command not used (reading returns zero) * Similar to the description of `sbf0 command flag' not used (reading returns zero)
Register Set 3: STATE registers ADMSTAT: ADM state register BASE + 4Ch Bit 15:9 Name Mode : read/write Description not used (reading returns zero) Read only. Writing does not affect this flag. 0: sub-blocks in adm are running 1: sub-blocks in adm are ready to accept "no clock". This flag is reset as zero when one or more of ADM sub-blocks are doing at least one pending action like external memory access. ADM should check if this flag is set before it issues system idle or software reset. 7:4 3 DRIAIF not used (reading returns zero) Data Region Invalid Access Interrupt Flag 0 : interrupt not issued, 1 : interrupt issued Program Region Invalid Access Interrupt Flag 0 : interrupt not issued, 1 : interrupt issued Sequential Buffer 1 Wrapping Interrupt Flag 0 : interrupt not issued, 1 : interrupt issued Sequential Buffer 0 Wrapping Interrupt Flag 0 : interrupt not issued, 1 : interrupt issued reset value : 0100h
8
ready_clk_down
2
PRIAIF
1
S1WIF
0
S0WIF
* Note: You can clear a specific bit of interrupt flags by writing a data to this register. It clears only the bit positions corresponding to those set to one in the written data. The bit positions corresponding to those that are set to zero in the written data remains as they are.
CACHESTAT: Cache status register
reset value : 0000h
40-22
CALMADM
FUNCTIONAL SPEC
BASE + 4Eh Bit [15:10] Name -
Mode : read only. Writing does not affect this register. Description not used (reading returns zero) 00: Undefined 01: I-Cache is in invalidation state. 10: I-Cache is in normal state. 11: I-Cache is in bypass state. not used (reading returns zero) 000: Undefined 001: X-Cache is in invalidation state. 010: X-Cache is in normal state. 011: X-Cache is in bypass state. 1xx: X-Cache is in flush state. not used (reading returns zero) * Similar to the description of `xc command flag'
[9:8]
ic state flag
[7]
-
[6:4]
xc state flag
[3] [2:0]
yc state flag
SBFSTAT: Sequential buffer status register BASE + 50h Bit [15] Name Mode : read only. Writing does not affect this register. Description not used (reading returns zero)
reset value : 0000h
[14:12]
sbf0 state flag
000: Sequential buffer 0 is in non-sequential access mode 001: Sequential buffer 0 is being filled 010: Sequential buffer 0 is being flushed 100: Sequential buffer 0 is in initialized mode 101: Sequential buffer 0 is in sequential read mode 110: Sequential buffer 0 is in sequential write mode others: undefined not used (reading returns zero) * Similar to the description of `sbf0 state flag' not used (reading returns zero)
[11] [10:8] [7:0]
sbf1 state flag -
Register Set 4: Sequential Buffer Function Registers SBL0OFF_H: Higher bits of offset register of sequential block 0 area BASE + 52h Mode : read/write reset value : 0000h
40-23
FUNCTIONAL SPEC
CALMADM
Bit [15:2] [1:0]
Name sbl0off_h
Description not used (reading returns zero) Higher 2 bits of 18-bit sequential block 0 offset (SBL0OFF[17:16]) reset value : 0000h
SBL0OFF_L: lower bits of offset register of sequential block 0 area BASE + 54h Bit [15:2] [1] [0] Name sbl0off_l sbl0off_1 sbl0off_0 Mode : read/write Description
Middle 14 bits of 18-bit sequential block 0 offset (SBL0OFF[15:2]) SBL0OFF[1]. Its is fixed to 0 when SBF0 is working in 32-bit access mode. SBL0OFF[0]. Its is fixed to 0.
* Note: When SBL0OFF is written SBL0OFF[1:0] is set as `00' because the boundary of SBL0 was fixed to be word (32-bit data) aligned for efficient system memory access.
SBL1OFF_H: Higher bits of offset register of sequential block 1 area BASE + 56h Bit [15:2] [1:0] Name Sbl1off_h Mode : read/write Description not used (reading returns zero)
reset value : 0000h
Higher 2 bits of 18-bit sequential block 1 offset (SBL1OFF[17:16]) reset value : 0000h
SBL1OFF_L: lower bits of offset register of sequential block 1 area BASE + 58h Bit [15:2] [1] [0] Name Sbl1off_l Sbl1off_1 Sbl1off_0 Mode : read/write Description
Middle 14 bits of 18-bit sequential block 1 offset (SBL1OFF[15:2]) SBL1OFF[1]. Its is fixed to 0 when SBF1 is working in 32-bit access mode. SBL1OFF[0]. Its is fixed to 0.
* Note: When SBL1OFF is written SBL1OFF[1:0] is set as `00' because the boundary of SBL1 was fixed to be word (32-bit data) aligned for efficient system memory access.
SBL0BEGIN_H: Higher bits of begin offset of sequential block 0 area in ring mode BASE + 5Ah Mode : read/write
reset value : 0000h
40-24
CALMADM
FUNCTIONAL SPEC
Bit [15:2] [1:0]
Name sbl0begin_h
Description not used (reading returns zero) Higher 2 bits of 18-bit sequential block 0 begin offset (SBL0BEGIN[17:16]) reset value : 0000h
SBL0BEGIN_L: lower bits of begin offset of sequential block 0 area in ring mode BASE + 5Ch Bit [15:2] [1:0] Name sbl0begin_l sbl0begin_10 Mode : read/write Description
Middle 14 bits of 18-bit sequential block 0 begin offset (SBL0BEGIN[15:2]) Lower 2 bits of 18-bit sequential block 0 begin offset (SBL0BEGIN[1:0]). These are fixed to 00.
SBL1BEGIN_H: Higher bits of begin offset of sequential block 1 area in ring mode BASE + 5Eh Bit [15:2] [1:0] Name Sbl1begin_h Mode : read/write Description not used (reading returns zero)
reset value : 0000h
Higher 2 bits of 18-bit sequential block 1 begin offset (SBL1BEGIN[17:16]) reset value : 0000h
SBL1BEGIN_L: lower bits of begin offset of sequential block 1 area in ring mode BASE + 60h Bit [15:2] [1:0] Name Sbl1begin_l Sbl1begin_10 Mode : read/write Description
Middle 14 bits of 18-bit sequential block 1 begin offset (SBL1BEGIN[15:2]) Lower 2 bits of 18-bit sequential block 1 begin offset (SBL1BEGIN[1:0]). These are fixed to 00.
SBL0END_H: Higher bits of end offset of sequential block 0 area in ring mode BASE + 62h Bit [15:2] [1:0] Name sbl0end_h Mode : read/write Description not used (reading returns zero)
reset value : 0000h
Higher 2 bits of 18-bit sequential block 0 end offset (SBL0END[17:16]) reset value : 0000h
SBL0END_L: lower bits of end offset of sequential block 0 area in ring mode
40-25
FUNCTIONAL SPEC
CALMADM
BASE + 64h Bit [15:2] [1:0] Name sbl0end_l sbl0end_10
Mode : read/write Description Middle 14 bits of 18-bit sequential block 0 end offset (SBL0END[15:2]) Lower 2 bits of 18-bit sequential block 0 end offset (SBL0END[1:0]). These are fixed to 00.
SBL1END_H: Higher bits of end offset of sequential block 1 area in ring mode BASE + 66h Bit [15:2] [1:0] Name Sbl1end_h Mode : read/write Description not used (reading returns zero)
reset value : 0000h
Higher 2 bits of 18-bit sequential block 1 end offset (SBL1END[17:16]) reset value : 0000h
SBL1END_L: lower bits of end offset of sequential block 1 area in ring mode BASE + 68h Bit [15:2] [1:0] Name Sbl1end_l Sbl1end_10 Mode : read/write Description
Middle 14 bits of 18-bit sequential block 1 end offset (SBL0END[15:2]) Lower 2 bits of 18-bit sequential block 1 end offset (SBL0END[1:0]). These are fixed to 00.
Register Set 5: SFRSI Function Registers SFRBSTAT0/1/2: SFR buffer state register BASE + 6Ah, 70h, 76h Bit [15:13] [12] [11:9] Name sfrbvalid Mode : read/write Description not used (reading returns zero) This flag is set as high only when SFR buffer contains valid read/write data. not used (reading returns zero) 0: read mode 1: write mode This flag is effective only when sfrbvalid flag is set as high. [7:6] not used (reading returns zero) reset value : 0xxxh
[8]
sfrbmode
40-26
CALMADM
FUNCTIONAL SPEC
[5:0]
Sfrbtag[21:16]
Higher 6 bits of SFR buffer tag address
SFRBTAG0/1/2: SFR tag address register BASE + 6Ch, 72h, 78h Bit [15:0] Name Sfrbtag[15:0] Mode : read/write Description Lower 16 bits of SFR buffer tag address
reset value : xxxxh
SFRBUF0/1/2: SFR data register BASE + 6Eh, 74h, 7Ah Bit [15:0] Name Sfrbuf Mode : read/write Description SFR data buffer
reset value : xxxxh
Register Set 6: DHCLK Control DHCLK_CON: DHCLK delay control register BASE + 7Ch Bit [15:3] [2:0] Name Dhclk_con Mode : read/write Description not used (reading returns zero) DHCLK (clock of I-Cache memories) delay control value reset value : 0000h
3
3-1
CalmADM3 Hardware Specifications
Interface Spec.
40-27
FUNCTIONAL SPEC
CALMADM
3-1-1 pin descriptions
Table 3-1. CalmADM3 Pin Description Group System Interface Signal nRES MCLK nSYSID DA[4:0] PMODE nIRQ nFIQ nEXPACK HBUSREQM HGRANTM HREADYM HADDRM [31:0] HTRANSM [1:0] HBURSTM [3:0] HSIZEM [2:0] HWRITEM HWDATAM[31:0] HRDATAM[31:0] nTRST TCK TMS TDI TDO nres_dbu runst_dbu BISTMODE MEMSEL[2:0] BCLK BIST_ON DIAG_BIST_XYC DONE_BIST_XYC ERROB_BIST_XYC PAUSE_BIST_XYC DIAG_BIST_IC DONE_BIST_IC ERROB_BIST_IC PAUSE_BIST_IC SCAN_TEST_MODE SCAN_ENABLE SCAN_IN direction I I O O O I I O O I I O O O O O O I I I I I O O O I I I I O O O O O O O O I I I polarity low rising low high low low low high high high high low rising low high high high high Description reset signal clock SYS command indicator DA output for SYS commands Privileged mode indicator Interrupt request Fast interrupt request Acknowledge for exceptions
AHB Master Interface
Debug Interface
Reset signal from DBU in ADM Indicating Calm is not stopped by DBU BIST input signals
BIST Interface
BIST output signals for X and Y-Cache memories
BIST output signals for I-Cache memories
Scan Test Interface
40-28
CALMADM
FUNCTIONAL SPEC
SCAN_OUT
O
-
3-1-2 pin timing diagrams
*WILL BE AVAILABLE IN LATER RELEASE IF NECESSARY
3-2
FEATURES
Arbiter
Prioritized scheduling of bus requests from 8 sources SFRSI (the highest priority) > SBF0 > SBF1 > X-Cache > Y-Cache > I-Cache > X-Cache Write-Back > Y-Cache Write-Back (the lowest priority)
3-3
FEATURES -
AHBMIU (AHB Master Interface Unit)
eight burst word access to system memory for I-Cache six burst word access to system memory for X/Y-Caches single burst half-word and byte access to system memory for cache bypass mode. One ~ four burst word access for sequential accesses to sequential blocks Single burst half-word access for random accesses to sequential blocks Single burst word access to SFRS
40-29
FUNCTIONAL SPEC
CALMADM
3-4
OVERVIEW
INSTRUCTION CACHE
I-Cache is a direct-mapped, 128x16-instruction size cache. Three commands, on, off and all-invalidation, are supported for normal cache function. Before I-Cache on, allinvalidation command should be done. I-Cache also supports one-line-invalidation function for debugging convenience. If Calm performs LDC instruction while `ldcinv' flag of ADMCFG register is on, one I-Cache line selected by program address of Calm is invalidated. Since I-Cache performs caching with virtual address (Calm program memory address), it is need to convert to physical address (system memory address). This conversion is done inside of I-Cache by adding cache address with the BASE field of corresponding region configuration register (R0CFG ~ R7CFG).
FEATURES Direct-mapped cache 128 data entries (cache lines) 256-bit wide data memory (16 half-word instructions in a cache line) 11-bit wide tag memory (10-bit tag address + 1 valid bit) 24-bit base fields for mapping to physical address Supports all invalidation and one line invalidation
3-5
DATA CACHES
In ADM are two data caches. One is X-Cache caching data in MAC X area. The other is Y-Cache caching data in MAC Y area. Since, X-Cache and Y-Cache are exactly same, only X-Cache is described more detail in this section. These two data caches also works as the data cache for Calm area as a kind of 4-way set-associative cache.
3-5-1
OVERVIEW
X-Cache
X-Cache is a 2-way set associative cache with a set sized 128x8-data.
40-30
CALMADM
FUNCTIONAL SPEC
Four commands, on, off, invalidation and flush, are supported for normal cache function. Before X-Cache on, allinvalidation command should be done. After X-Cache off, flush command should be done to keep system memory data consistency. Since X-Cache performs caching with virtual address (MAC X memory address), it is need to be converted to physical address (Host memory address). The physical address is an addition of 4:3 reduced virtual address with X-area base (XBASE). X-Cache works as not only the cache for MAC X area data accessed by both Calm and Mac but also the cache for Calm area data accessed by Calm only.
FEATURES
2-way set associative cache 128 data entries (cache lines) in a set 8 audwords (192 bit) in a cache line only 128 bits of 192-bit cache line are used as Calm area cache 24-bit wide Cache Tag Memory ((11-bit tag address + 1 valid bit) * 2 sets) 256 dirty flags (for 128 lines * 2 sets) 24-bit base fields for mapping to physical address Supports invalidation and flushing.
3-5-2
OVERVIEW
X/Y-Cache as calm area data cache
X/Y-Caches work as not only the cache for MAC X/Y area data accessed by both Calm and Mac but also the cache for Calm area data accessed by Calm only. By setting XYRR code in ADMCFG register properly, X- and YCache can be enabled/disabled as the cache of Calm. Since X/Y-Caches perform caching with virtual address (Calm data memory address), virtual address to physical address (Host memory address) conversion is needed. This conversion is done inside of X/Y-Cache by adding cache address with the BASE field of corresponding region configuration register (R8CFG ~ R11CFG).
OPERATIONS When X/Y-Caches work as the cache for Calm area data, the operation is depends on the value of XYRR bits in ADMCFG register. When X-Cache is selected (XYRR == 01) Calm area data are accessed through X-Cache block whether its cache function is enabled or not.
40-31
FUNCTIONAL SPEC
CALMADM
-
When Y-cache is selected (XYRR == 1x) Calm area data are accessed through Y-Cache block whether its cache function is enabled or not.
-
When Round robin scheme is selected (XYRR == 00) If both of X- and Y- Caches are enabled, X- and Y-Cache are selected for cache data replacement one after another (round robin). At the first miss, X-Cache is selected for replacement. When next miss occurred, Y-Cache is selected for replacement. At the next miss, X-cache is selected, and so on. If both of X- and Y- Caches are disabled, Calm area data are accessed through Y-Cache block. If one of X- and Y- Caches is enabled and the other one is disabled, Calm area data are accessed through enabled Cache block.
ARCHITECTURE When X/Y-Caches work as the cache for Calm area data, the architecture of the cache is depends on the value of XYRR bits in ADMCFG register. Following description is for the case when both X- and Y- caches are enabled. When one of X- or Y-Cache is selected (XYRR == 01 or XYRR == 1x) 4K byte, 2-way set associative cache 128 data entries (cache lines) in a set 8 half-words (128 bit) in a cache line When Round robin scheme is selected (XYRR == 00) 8K byte, 4-way set associative cache 128 data entries (cache lines) in a set 8 half-words (128 bit) in a cache line
3-6
OVERVIEW
SBFU (S-buffer unit)
In ADM, two sequential buffers, SBF0 and SBF1, are included. A sequential buffer consists of a 128-bit FIFO, a 18-bit offset register, two 18-bit boundary offset registers and a 16-bit data buffer. 128-bit FIFO is used as buffer when Mac sequentially accesses sequential block. A 16-bit data register is used as buffer when Calm randomly accesses sequential block. 18-bit offset register contains offset address of sequential block data to be accessed. Since it is defined in HFRS, user can write the start address of sequential block into
40-32
CALMADM
FUNCTIONAL SPEC
this register. This register is added with BASE field of the region configuration register (S0CFG, S1CFG) to generate physical address of sequential data. After a sequential access to sequential block has done, this register value is increased automatically. This increment is modulated by the size limit defined in SIZE field of the region configuration register (S0CFG, S1CFG). In ring mode, auto-incremented register value is compared with 18-bit end offset register value. If these are same, offset register is set as 18-bit begin offset register value and interrupt flag in ADMSTAT register is set. Two special commands, fill and flush, are supported for a sequential buffer. Before user starts sequential read on sequential block, fill command should be done. Flush command should be done after sequential writes end. Access mode, unit data size and data size conversion scheme in a SBFU are defined in ADMCFG register. More of SBFU operation is described in 2-2.
FEATURES 4-word FIFO used as a sequential buffer 18-bit offset address register : automatically increased during sequential accesses : the increment is modulated according to the SIZE field 16-bit data buffer for random access to sequential block area Fill and Flush commands Unit data size and data size conversion scheme selected by setting control flags. Two access modes supported (linear mode and ring mode) Two boundary offset registers (begin offset and end offset) are used in the ring mode.
-
3-7
FEATURES -
SFRSI (SFRS interface unit)
One-entry cache composed of : SFRBUF[15:0]: SFR read/write Buffer : SFRBTAG[21:0]: SFRBUF tag address : SFRBVALID: "0" - invalid, "1" - valid : SFRBMODE: "0" - read mode, "1" - write mode One-entry cache with : auto-invalidation on hit : auto-backup on exception : recovery on `sys_rsfrb' command Backup stack : depth = 2 (for two exceptions, IRQ and FIQ)
-
-
40-33
FUNCTIONAL SPEC
CALMADM
: contains all components of the one-entry cache All registers and flags in the one-entry cache and the stack are defined in HFRS : for debugging and context switching purpose
4
4-1
Constraints on using CalmADM3
*NOTE: THIS CHAPTER IS EXACTLY SAME AS THE ONE IN CALMADM2 SPECIFICATION. IF YOU ARE FAMILIAR WITH CALMADM2, YOU DON'T NEED TO READ THIS CHAPTER.
Constraints on using CalmRISC16F
DELAY SLOT INSTRUCTION As an instruction at delay slot, following 3 types of instructions are prohibited. - Break instruction - Branch instructions - two word instructions
4-2
Constraints on using CalmMAC24F
LOADING RAM POINTER Because of the nature of pipeline scheme and data memory accessing scheme of Mac, data memory accessing with the RAM pointer, that is loaded from the outside of Mac just before, is prohibited. An ENOP instruction or another instruction should be inserted between RAM pointer load instruction and data memory access instruction using that RAM pointer as data address. Instructions loading RAM pointer are listed in table6-1. Example code ELD RP0, RPD1.0 ENOP ELD A, @RP0 ; load RAM pointer ; inserted ENOP ; using loaded RAM pointer as data address
40-34
CALMADM
FUNCTIONAL SPEC
Table 6-1. list of instructions loading RAM pointers opc ELD Note. op1 rpui op2 rpd1.adr:2 Function op1<-op2 Flag -
opc - opcode, opi- operand i
ACCESSING MIN/MAX DATA For easy searching MIN/MAX data, Mac offers special instructions, EMIN and EMAX. The example code below shows how to search MIN/MAX data with EMIN/EMAX instructions. After the execution of a EMIN/EMAX instruction, the address of MIN/MAX data is latched in RP3. Because of the nature of pipeline scheme and data memory accessing scheme of Mac, data memory accessing with RP3, that is latched by execution of EMIN/EMAX instruction just before, is prohibited. An ENOP instruction or another instruction should be inserted between EMIN/EMAX instruction and data memory access instruction using RP3 as data address. EMIN/EMAX Instructions are listed in table6-2. Example code ELD C, @RP0+S0 Loop-start: EMAX A, C, C, @RP0+S0 JP Loop_start EMAX A, C ENOP ELD A, @RP3 ; 1st data load ; 1st MAX evaluation, 2nd data load ; last MAX evaluation ; inserted ENOP ; using RP3 as data address
Table 6-2. list of EMIN/EMAX instructions opc EMAX Ai EMIN Note. opc - opcode, opi- operand i Ci Ci @rps Ai<-min(Ai,Ci), op3<-op4, RP3<- address V,N,Z,C op1 op2 op3 op4 Function Ai<-max(Ai,Ci), op3<-op4, RP3<-address Flag V,N,Z,C
4-3
Constraints on accessing sequential buffers
DATA ALIGNMENT
40-35
FUNCTIONAL SPEC
CALMADM
When Calm accesses sequential block area, the data can be byte or half word. When Mac access sequential buffer, the data can be half word aligned or word aligned. However, when fill or flush is performed in sequential buffer, ADM assumes the data is word aligned. This assumption was taken for efficient external memory access. When user accesses a sequential buffer in half word mode, odd number of sequential accesses causes miss-aligned external memory access. There is no hardware to prevent odd number of sequential accesses in ADM. Therefore, user program should consider data alignment, especially for sequential writes in half word mode. SBL0OFF and SBL1OFF can be half word aligned or word aligned when these are automatically increased. However, these are fixed to be word aligned when these are written. SBL0BEGIN, SBL0END, SBL1BEGIN are SBL1END are fixed to be word aligned.
CONFIRM FLUSH After a flush command is performed, it is recommended to check the status flag in SBFSTAT register if the flush has done physically. This status check is not needed in most cases. However, when ADM transmits certain data to Host processor through sequential buffer, data coherence may be corrupted if this confirmation is omitted.
4-4
Constraints on accessing X/Y-Caches
SETTING XYRR The XYRR flags in ADMCFG register should be set while both X-Cache and Y-Cache are turned off. If the XYRR flags are changed while one or both of X-Cache and Y-Cache are turned on, following data reads and writes may be performed incorrectly. Because of that, the data in system memory may corrupt.
4-5
Definitions of Abbreviations
Instruction tables in this chapter are extracted from "3.3 Quick Reference" instruction table in "CalmMAC24 DSP Coprocessor Architecture Reference Manual". Definition of abbreviations used in instruction tables is listed following tables. This tables are copy of "3.2 Instruction Coding, (1) Abbreviation Definition and Encoding" of "CalmMAC24 DSP Coprocessor Architecture Reference Manual".
rps
Mnemonic Encoding Description
40-36
CALMADM
FUNCTIONAL SPEC
RP0+S0 RP1+S0 RP2+S0 RP3+S0 RP0+S1 RP1+S1 RP2+S1 RP3+S1
000 001 010 011 100 101 110 111
RP0 post-modified by SD0 S0 field RP1 post-modified by SD1 S0 field RP2 post-modified by SD2 S0 field RP3 post-modified by SD3 S0 field RP0 post-modified by SD0 S1 field RP1 post-modified by SD1 S1 field RP2 post-modified by SD2 S1 field RP3 post-modified by SD3 S1 field
rpd
Mnemonic RP0+D0 RP1+D0 RP2+D0 RP3+D0 RP0+D1 RP1+D1 RP2+D1 RP3+D1 Encoding 000 001 010 011 100 101 110 111 Description RP0 post-modified by SD0 D0 field RP1 post-modified by SD1 D0 field RP2 post-modified by SD2 D0 field RP3 post-modified by SD3 D0 field RP0 post-modified by SD0 D1 field RP1 post-modified by SD1 D1 field RP2 post-modified by SD2 D1 field RP3 post-modified by SD3 D1 field
rp01s
Mnemonic RP0+S0 RP1+S0 RP0+S1 Encoding 00 01 10 Description RP0 post-modified by SD0 S0 field RP1 post-modified by SD1 S0 field RP0 post-modified by SD0 S1 field
40-37
FUNCTIONAL SPEC
CALMADM
RP1+S1
11
RP1 post-modified by SD1 S1 field
rp3s
Mnemonic RP3+S0 RP3+S1 Encoding 0 1 Description RP3 post-modified by SD3 S0 field RP3 post-modified by SD3 S1 field
mg1
Mnemonic Y0 Y1 X0 X1 MA0(H) MA0L MA1(H) MA1L Encoding 000 001 010 011 100 101 110 111 Description Y0[23:0] register Y1[23:0] register X0[23:0] register X1[23:0] register MA0[51:0] / MA0[47:24] register MA0[23:0] register MA1[51:0] / MA1[47:24] register MA1[23:0] register
mg2
Mnemonic RP0 RP1 RP2 RP3 RPD0 RPD1 Encoding 000 001 010 011 100 101 Description current bank RP0[15:0] register current bank RP1[15:0] register current bank RP2[15:0] register current bank RP3[15:0] register RPD0[15:0] register RPD1[15:0] register
40-38
CALMADM
FUNCTIONAL SPEC
MC0 MC1
110 111
MC0[15:0] register MC1[15:0] register
sdi
Mnemonic SD0 SD1 SD2 SD3 Encoding 00 01 10 11 Description current bank SD0[15:0] register (SD0 or SD0E) current bank SD1[15:0] register current bank SD2[15:0] register current bank SD3[15:0] register (SD3 or SD3E)
Ai
Mnemonic A B Encoding 0 1 Description A[23:0] register B[23:0] register
Ci
Mnemonic C D Encoding 0 1 Description C[23:0] register D[23:0] register
An
Mnemonic A B C D Encoding 00 01 10 11 Description A[23:0] register B[23:0] register C[23:0] register D[23:0] register
40-39
FUNCTIONAL SPEC
CALMADM
rpui
Mnemonic RP0 RP1 RP2 RP3 MC0_0 MC1_0 MC0_1 MC1_1 SD0_0 SD1_0 SD2_0 SD3_0 SD0_1 SD1_1 SD2_1 SD2_1 Encoding 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description current bank RP0[15:0] register current bank RP1[15:0] register current bank RP2[15:0] register current bank RP3[15:0] register MC0[15:0] register (set 0) MC1[15:0] register (set 0) MC0[15:0] register (set 1) MC1[15:0] register (set 1) current bank SD0[15:0] register (set 0) current bank SD1[15:0] register (set 0) current bank SD2[15:0] register (set 0) current bank SD3[15:0] register (set 0) current bank SD0[15:0] register (set 1) current bank SD1[15:0] register (set 1) current bank SD2[15:0] register (set 1) current bank SD3[15:0] register (set 1)
mga
Mnemonic MA0 MA1 A Encoding 00 01 10 Description MA0[51:0] / MA0[47:24] register MA1[51:0] / MA1[47:24] register A[23:0] register
40-40
CALMADM
FUNCTIONAL SPEC
B
11
B[23:0] register
mgx
Mnemonic Y0 Y1 X0 X1 Encoding 00 01 10 11 Description Y0[23:0] register Y1[23:0] register X0[23:0] register X1[23:0] register
5
5-1
Information for CalmShine Development
Simulator Spec.
MEMORY MAP Simulator should keep track of memory configuration in section 2-1 from Calm and Mac point of view. - Program regions, Calm regions, X/Y/S0/S1 regions can be modeled same as the CalmADM2 case. - Modeling the region control and the address translation to system memory space is not needed. - HFRS Registers can be modeled those read/write function only. Modeling precise functionality of them described in this document is not needed. - Exception: Some sequential buffer related registers (flags) should be modeled precisely as described in next paragraph. - SFRS area can be modeled as a normal memory area.
40-41
FUNCTIONAL SPEC
CALMADM
MODELING SEQUENTIAL BUFFERS
*NOTE: THIS SECTION IS EXACTLY SAME AS THE ONE IN CALMADM2 SPECIFICATION. IF YOU ARE FAMILIAR WITH CALMADM2, YOU DON'T NEED TO READ THIS SECTION.
Simulator should keep track of the sequential accesses in 2-2 in terms of the functionality only. Modeling exact hardware structure is not needed. Sequential buffer models are not needed in simulator. Sequential offset registers should be modeled in simulator. Being read/written as a control register, addressing sequential block area and auto-increment capability of these registers should be modeled. When written, these registers should be word-aligned. In other words, lower 2 bits of these registers should be forced as 0 when Calm writes values to these registers. When auto-incremented, the incrementing step should follow the mode defined by flags of ADMCFG register in HFRS. In ring mode, equivalence between offset register and end offset register should be checked in simulator. In addition, wrapping and flag setting should be done in simulator when those are same. Data format mapping defined by SBF0/1 mode flags should be modeled in simulator. SBF0/1 mode flags are part of ADMCFG register in HFRS. Modeling commands on sequential buffers, defined by SBFCON register in HFRS, is not needed in simulator. Access mode defined by [3] bits of SBF0/1 mode flags should be modeled in simulator. Begin offset registers and end offset registers should be modeled in simulator as one of memory mapped I/O registers. These should be used for wrapping operation of offset register in ring mode. When sbf0mode/sbf1mode flags are written, newly updated values are not effective to the operation of sequential buffers. New values are effective after the sequential buffer is newly initialized, which means that SBL0OFF/SBL1OFF registers are newly written.
-
5-2
Emulator Spec.
ACCESSING SFRS Because of hardware limitation of SFRSI block, SFRS area should be accessed in 16-bit mode only. Byte-read from SFRS area always returns zero. Byte-write to SFRS area is same as no-operation.
40-42
S5L840F (Preliminary Spec)
GPIO PORTS
10
OVERVIEW
GPIO PORTS
S5L840F has 72 multi-functional GPIO (general-purpose input/output) port pins organized into ten port groups: Each port can be easily configured by software to meet various system configuration and design requirements. These multi-functional pins need to be properly configured before their use. If a multiplexed pin is not used as a dedicated functional pin, this pin can be configured as GPIO ports. The initial pin states, before pin configurations, are configured elegantly to avoid some problems.
10-1
GPIO PORTS
S5L840F (Preliminary Spec)
Table 10-1. Port Configuration Overview Port 0 Function 1 Pin No. P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 38 39 40 41 31 32 42 43 GPIO Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Pin_name TACK/TACAP TAOUT TCCK SPDIF RX TX EINT6 EINT7 Selectable Pin Functions Function 2 I/O I O I O I O I I Module Timer Timer Timer SPDIF UART UART ICU ICU SDWP NF_RBN Function 3 Pin _name I/O - - - - - - I I SDC NF Module
Port 1 Function 1 Pin No. P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 108 109 110 115 116 117 10 11 GPIO Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output MOSI MISO SPICLK SCL SDA nSSI EINT4 EINT5 Pin _name
Selectable Pin Functions Function 2 I/O I/O I/O I/O I/O I/O I I I Module SPI SPI SPI IIC IIC SPI ICU ICU Function 3 Pin _name I/O - - - - - - - - Module
Port 2 Function 1 Pin No. P2.0 P2.1 P2.2 P2.3 48 49 50 51 GPIO Input/output Input/output Input/output Input/output EINT0 EINT1 EINT2 EINT3 Pin _name
Selectable Pin Functions Function 2 I/O I I I I Module ICU ICU ICU ICU Function 3 Pin _name I/O - - - - Module
10-2
S5L840F (Preliminary Spec)
GPIO PORTS
Table 10-1. Port Configuration Overview (Continued) Port 3 Function 1 Pin No. P3.0 P3.1 61 73 GPIO Input/output Input/output Pin_name CK_SDC_MM C CK_MS Selectable Pin Functions Function 2 I/O O O Module SDC/MMC MS Function 3 Pin _name I/O - - Module
Port 4 Function 1 Pin No. P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 P4.7 56 58 60 63 69 71 74 76 GPIO Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 Pin _name
Selectable Pin Functions Function 2 I/O I/O I/O I/O I/O I/O I/O I/O I/O Module SMC SMC SMC SMC SMC SMC SMC SMC Function 3 Pin _name I/O - - - - - - - - Module
Port 5 Function 1 Pin No. P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 P5.6 P5.7 57 59 62 64 70 72 75 77 GPIO Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output IO8 IO9 IO10 IO11 IO12 IO13 IO14 IO15 Pin _name
Selectable Pin Functions Function 2 I/O I/O I/O I/O I/O I/O I/O I/O I/O Module SMC SMC SMC SMC SMC SMC SMC SMC D0 BS D1 D0 CMD D3 D2 Function 3 Pin _name I/O - - - - - - - - MS MS Module SDC/MMC SDC SDC/MMC SDC SDC
10-3
GPIO PORTS
S5L840F (Preliminary Spec)
Table 10-1. Port Configuration Overview (Continued) Port 6 Function 1 Pin No. P6.0 P6.1 P6.2 P6.3 P6.4 P6.5 P6.6 P6.7 78 79 80 81 82 83 84 85 GPIO Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output nRE nCE0 nCE1 nCE2 CLE ALE nWE nWP Pin_name Selectable Pin Functions Function 2 I/O O O O O O O O O Module SMC SMC SMC SMC SMC SMC SMC SMC Function 3 Pin _name I/O - - - - - - - - Module
Port 7 Function 1 Pin No. P7.0 P7.1 P7.2 P7.3 P7.4 86 87 90 91 92 GPIO Input/output Input/output Input/output Input/output Input/output SDI WS SDO SCLK MCLK Pin _name
Selectable Pin Functions Function 2 I/O I O O O O Module IIS IIS IIS IIS IIS Function 3 Pin _name I/O - - - - - Module
Port 8 Function 1 Pin No. P8.0 P8.1 P8.2 P8.3 P8.4 P8.5 P8.6 P8.7 18 24 25 26 27 28 29 30 GPIO Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 Pin _name
Selectable Pin Functions Function 2 I/O O O O O O O O O Module LCD LCD LCD LCD LCD LCD LCD LCD Function 3 Pin _name I/O - - - - - - - - Module
10-4
S5L840F (Preliminary Spec)
GPIO PORTS
Table 10-1. Port Configuration Overview (Continued) Port 9 Function 1 Pin No. P9.0 P9.1 P9.2 P9.3 P9.4 33 34 35 36 37 GPIO Input/output Input/output Input/output Input/output Input/output RE WE CS REG RESET Pin _name Selectable Pin Functions Function 2 I/O O O O O O Module LCD LCD LCD LCD LCD Function 3 Pin _name I/O - - - - - Module
Port 10 Function 1 Pin No. P10.0 P10.1 P10.2 P10.3 P10.4 P10.5 P10.6 P10.7 93 94 95 96 104 105 106 107 GPIO Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Pin _name
Selectable Pin Functions Function 2 I/O - - - - - - - - Module Function 3 Pin _name I/O - - - - - - - - Module
10-5
GPIO PORTS
S5L840F (Preliminary Spec)
PORT CONTROL DESCRIPTIONS Port Configuration Register (PCON0 - PCON10) In S5L840F, most pins are multiplexed, and the PCONn (port control register) determines which function is used for each pin. If P0.6-P0.7 is used for the wakeup signal in power down mode, these ports must be configured for interrupt mode. Port Data Register (PDAT0 - PDAT10) If Ports are configured as output ports, data can be written to the corresponding bit of PDATn. If Ports are configured as input ports, the data can be read from the corresponding bit of PDATn. External Interrupt Control Register The 8 external interrupts support various trigger mode: the trigger mode can be configured as falling-edge trigger and rising-edge trigger. Because each external interrupt pin has an integrated digital noise filter, the interrupt controller can recognize the request signal that lasts longer than 3 clocks.
10-6
S5L840F (Preliminary Spec)
GPIO PORTS
GPIO PORT SPECIAL FUNCTION REGISTERS
PORT 0 CONTROL REGISTERS (PCON0, PDAT0) Register PCON0 PDAT0 Address 0x3CF0 0000 0x3CF0 0004 R/W R/W R/W Description Configures the pins of port 0 The data register for port 0 Reset Value 0x0000 0000 Undefined
PCON0 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7
Bit [1:0] [3:2] [5:4] [7:6] [9:8] [11:10] [13:12] [15:14]
Description 00 = Input 01 = Output 10 = TACK/TACAP(Timer) 11 = Not used 00 = Input 10 = TAOUT(Timer) 00 = Input 10 = TCCK(Timer) 00 = Input 10 = SPDIF(SPDIF) 00 = Input 10 = RX(UART) 00 = Input 10 = TX(UART) 00 = Input 10 = EINT6(ICU) 00 = Input 10 = EINT7(ICU) 01 = Output 11 = Not used 01 = Output 11 = Not used 01 = Output 11 = Not used 01 = Output 11 = Not used 01 = Output 11 = Not used 01 = Output 11 = SDWP(SDC) 01 = Output 11 = NF_RBN(SMC)
PDAT0 P0[7:0]
Bit [7:0]
Description When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read.
10-7
GPIO PORTS
S5L840F (Preliminary Spec)
PORT 1 CONTROL REGISTERS (PCON1, PDAT1) Register PCON1 PDAT1 Address 0x3CF0 0010 0x3CF0 0014 R/W R/W R/W Description Configures the pins of port 1 The data register for port 1 Reset Value 0x0000 0000 Undefined
PCON1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7
Bit [1:0] [3:2] [5:4] [7:6] [9:8] [11:10] [13:12] [15:14] 00 = Input 10 = MOSI(SPI) 00 = Input 10 = MISO(SPI) 00 = Input 10 = SPICLK(SPI) 00 = Input 10 = SCL(IIC:Open Drain) 00 = Input 10 = SDA(IIC:Open Drain) 00 = Input 10 = nSSI(SPI) 00 = Input 10 = EINT4(ICU) 00 = Input 10 = EINT5(ICU)
Description 01 = Output 11 = Not used 01 = Output 11 = Not used 01 = Output 11 = Not used 01 = Output 11 = Not used 01 = Output 11 = Not used 01 = Output 11 = Not used 01 = Output 11 = Not used 01 = Output 11 = Not used
PDAT1 P1[7:0]
Bit [7:0]
Description When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read.
10-8
S5L840F (Preliminary Spec)
GPIO PORTS
PORT 2 CONTROL REGISTERS (PCON2, PDAT2) Register PCON2 PDAT2 Address 0x3CF0 0020 0x3CF0 0024 R/W R/W R/W Description Configures the pins of port 2 The data register for port 2 Reset Value 0x0000 0000 Undefined
PCON2 P2.0 P2.1 P2.2 P2.3
Bit [1:0] [3:2] [5:4] [7:6] 00 = Input 10 = EINT0(ICU) 00 = Input 10 = EINT1(ICU) 00 = Input 10 = EINT2(ICU) 00 = Input 10 = EINT3(ICU)
Description 01 = Output 11 = Not used 01 = Output 11 = Not used 01 = Output 11 = Not used 01 = Output 11 = Not used
PDAT2 P2[3:0]
Bit [3:0]
Description When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read.
10-9
GPIO PORTS
S5L840F (Preliminary Spec)
PORT 3 CONTROL REGISTERS (PCON3, PDAT3) Register PCON3 PDAT3 Address 0x3CF0 0030 0x3CF0 0034 R/W R/W R/W Description Configures the pins of port 3 The data register for port 3 Reset Value 0x0000 0000 Undefined
PCON3 P3.0 P3.1
Bit [1:0] [3:2]
Description 00 = Input 01 = Output 10 = CK_SDC(SDC/MMC) 11 = Not used 00 = Input 10 = CK_MS(MS) 01 = Output 11 = Nout used
PDAT3 P3[1:0]
Bit [1:0]
Description When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read.
10-10
S5L840F (Preliminary Spec)
GPIO PORTS
PORT 4 CONTROL REGISTERS (PCON4, PDAT4) Register PCON4 PDAT4 Address 0x3CF0 0040 0x3CF0 0044 R/W R/W R/W Description Configures the pins of port 4 The data register for port 4 Reset Value 0x0000 0000 Undefined
PCON4 P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 P4.7
Bit [1:0] [3:2] [5:4] [7:6] [9:8] [11:10] [13:12] [15:14] 00 = Input 10 = IO0(SMC) 00 = Input 10 = IO1(SMC) 00 = Input 10 = IO2(SMC) 00 = Input 10 = IO3(SMC) 00 = Input 10 = IO4(SMC) 00 = Input 10 = IO5(SMC) 00 = Input 10 = IO6(SMC) 00 = Input 10 = IO7(SMC)
Description 01 = Output 11 = Not used 01 = Output 11 = Not used 01 = Output 11 = Not used 01 = Output 11 = Not used 01 = Output 11 = Not used 01 = Output 11 = Not used 01 = Output 11 = Not used 01 = Output 11 = Not used
PDAT4 P4[7:0]
Bit [7:0]
Description When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read.
10-11
GPIO PORTS
S5L840F (Preliminary Spec)
PORT 5 CONTROL REGISTERS (PCON5, PDAT5) Register PCON5 PDAT5 Address 0x3CF0 0050 0x3CF0 0054 R/W R/W R/W Description Configures the pins of port 5 The data register for port 5 Reset Value 0x0000 0000 Undefined
PCON5 P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 P5.6 P5.7
Bit [1:0] [3:2] [5:4] [7:6] [9:8] [11:10] [13:12] [15:14] 00 = Input 10 = IO8(SMC) 00 = Input 10 = IO9(SMC) 00 = Input 10 = IO10(SMC) 00 = Input 10 = IO11(SMC) 00 = Input 10 = IO12(SMC) 00 = Input 10 = IO13(SMC) 00 = Input 10 = IO14(SMC) 00 = Input 10 = IO15(SMC)
Description 01 = Output 11 = D1(SDC/MMC) 01 = Output 11 = D0(SDC) 01 = Output 11 = CMD(SDC/MMC) 01 = Output 11 = D3(SDC) 01 = Output 11 = D2(SDC) 01 = Output 11 = Not used 01 = Output 11 = D0(MS) 01 = Output 11 = BS(MS)
PDAT5 P5[7:0]
Bit [7:0]
Description When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read.
10-12
S5L840F (Preliminary Spec)
GPIO PORTS
PORT 6 CONTROL REGISTERS (PCON6, PDAT6) Register PCON6 PDAT6 Address 0x3CF0 0060 0x3CF0 0064 R/W R/W R/W Description Configures the pins of port 6 The data register for port 6 Reset Value 0x0000 0000 Undefined
PCON6 P6.0 P6.1 P6.2 P6.3 P6.4 P6.5 P6.6 P6.7
Bit [1:0] [3:2] [5:4] [7:6] [9:8] [11:10] [13:12] [15:14] 00 = Input 10 = nRE(SMC) 00 = Input 10 = nCE0(SMC) 00 = Input 10 = nCE1(SMC) 00 = Input 10 = nCE2(SMC) 00 = Input 10 = CLE(SMC) 00 = Input 10 = ALE(SMC) 00 = Input 10 = nWE(SMC) 00 = Input 10 = nWP(SMC)
Description 01 = Output 11 = Not used 01 = Output 11 = Not used 01 = Output 11 = Not used 01 = Output 11 = Not used 01 = Output 11 = Not used 01 = Output 11 = Not used 01 = Output 11 = Not used 01 = Output 11 = Not used
PDAT6 P6[7:0]
Bit [7:0]
Description When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read.
10-13
GPIO PORTS
S5L840F (Preliminary Spec)
PORT 7 CONTROL REGISTERS (PCON7, PDAT7) Register PCON7 PDAT7 Address 0x3CF0 0070 0x3CF0 0074 R/W R/W R/W Description Configures the pins of port 7 The data register for port 7 Reset Value 0x0000 0000 Undefined
PCON7 P7.0 P7.1 P7.2 P7.3 P7.4
Bit [1:0] [3:2] [5:4] [7:6] [9:8] 00 = Input 10 = SDI(IIS) 00 = Input 10 = WS(IIS) 00 = Input 10 = SDO(IIS) 00 = Input 10 = SCLK(IIS) 00 = Input(EINT4) 10 = MCLK(IIS)
Description 01 = Output 11 = Not used 01 = Output 11 = Not used 01 = Output 11 = Not used 01 = Output 11 = Not used 01 = Output 11 = Not used
PDAT7 P7[4:0]
Bit [4:0]
Description When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read.
10-14
S5L840F (Preliminary Spec)
GPIO PORTS
PORT 8 CONTROL REGISTERS (PCON8, PDAT8) Register PCON8 PDAT8 Address 0x3CF0 0080 0x3CF0 0084 R/W R/W R/W Description Configures the pins of port 8 The data register for port 8 Reset Value 0x0000 0000 Undefined
PCON8 P8.0 P8.1 P8.2 P8.3 P8.4 P8.5 P8.6 P8.7
Bit [1:0] [3:2] [5:4] [7:6] [9:8] [11:10] [13:12] [15:14] 00 = Input 10 = LD0(LCD) 00 = Input 10 = LD1(LCD) 00 = Input 10 = LD2(LCD) 00 = Input 10 = LD3(LCD) 00 = Input 10 = LD4(LCD) 00 = Input 10 = LD5(LCD) 00 = Input 10 = LD6(LCD) 00 = Input 10 = LD7(LCD)
Description 01 = Not used 11 = Not used 01 = Not used 11 = Not used 01 = Not used 11 = Not used 01 = Not used 11 = Not used 01 = Not used 11 = Not used 01 = Not used 11 = Not used 01 = Not used 11 = Not used 01 = Not used 11 = Not used
PDAT8 P8[7:0]
Bit [3:0]
Description When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read.
10-15
GPIO PORTS
S5L840F (Preliminary Spec)
PORT 9 CONTROL REGISTERS (PCON9, PDAT9) Register PCON9 PDAT9 Address 0x3CF0 0090 0x3CF0 0094 R/W R/W R/W Description Configures the pins of port 9 The data register for port 9 Reset Value 0x0000 0000 Undefined
PCON5 P9.0 P9.1 P9.2 P9.3 P9.4
Bit [1:0] [3:2] [5:4] [7:6] [9:8] 00 = Input 10 = RE(LCD) 00 = Input 10 = WE(LCD) 00 = Input 10 = CS(LCD) 00 = Input 10 = REG(LCD) 00 = Input 10 = RESET(LCD)
Description 01 = Output 11 = Not used 01 = Output 11 = Not used 01 = Output 11 = Not used 01 = Output 11 = Not used 01 = Output 11 = Not used
PDAT5 P9[4:0]
Bit [4:0]
Description When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read.
10-16
S5L840F (Preliminary Spec)
GPIO PORTS
PORT 10 CONTROL REGISTERS (PCON10, PDAT10) Register PCON10 PDAT10 Address 0x3CF0 00A0 0x3CF0 00A4 R/W R/W R/W Description Configures the pins of port 5 The data register for port 5 Reset Value 0x0000 0000 Undefined
PCON5 P10.0 P10.1 P10.2 P10.3 P10.4 P10.5 P10.6 P10.7
Bit [1:0] [3:2] [5:4] [7:6] [9:8] [11:10] [13:12] [15:14] 00 = Input 1x = Not used 00 = Input 1x = Not used 00 = Input 1x = Not used 00 = Input 1x = Not used 00 = Input 1x = Not used 00 = Input 1x = Not used 00 = Input 1x = Not used 00 = Input 1x = Not used
Description 01 = Output 01 = Output 01 = Output 01 = Output 01 = Output 01 = Output 01 = Output 01 = Output
PDAT5 P10[7:0]
Bit [7:0]
Description When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read.
10-17
GPIO PORTS
S5L840F (Preliminary Spec)
EINTPOL (EXTERNAL INTERRUPT POLARITY CONTROL REGISTER) The EXTINTR register selects the trigger types among various level or edge trigger mode of the external interrupt. Register EXTPOL EXTINTR P2.0/INT0 Address 0x39C0 0018 Bit [0] Trigger mode of the EXTINT0. 0 = Falling edge triggered 1 = Rising edge triggered Trigger mode of the EXTINT1. 0 = Falling edge triggered 1 = Rising edge triggered Trigger mode of the EXTINT2. 0 = Falling edge triggered 1 = Rising edge triggered Trigger mode of the EXTINT3. 0 = Falling edge triggered 1 = Rising edge triggered Trigger mode of the EXTINT4. 0 = Falling edge triggered 1 = Rising edge triggered Trigger mode of the EXTINT5. 0 = Falling edge triggered 1 = Rising edge triggered Trigger mode of the EXTINT6. 0 = Falling edge triggered 1 = Rising edge triggered Trigger mode of the EXTINT7. 0 = Falling edge triggered 1 = Rising edge triggered R/W R/W Description External Interrupt control register Description Reset Value 0x0000 0000
P2.1/INT1
[1]
P2.2/INT2
[2]
P2.3/INT3
[3]
P1.6/INT4
[4]
P1.7/INT5
[5]
P0.6/INT6
[6]
P0.7/INT7
[7]
NOTES: 1. Because each external interrupt pins has a digital filter, the interrupt controller can recognize a request signal that is longer than 3 clocks. 2. If users want to change the trigger mode in the external interrupt mode, users are first required to switch the corresponding pin to input mode and then change the trigger mode.
10-18
S5L840F (Preliminary Spec)
GPIO PORTS
NOTES
10-19
ICU PRELIMINARY SPECIFICATION
S5L840FX FLASH TYPE MP3 DECODER
ICU (Interrupt Control Unit)
USER'S MANUAL REV0.0
Kim, Hye-Ryeong MEDIA Player PJ System LSI Business Device Solution Network Division Samsung Electronics
30-1
ICU PRELIMINARY SPECIFICATION
S5L840FX FLASH TYPE MP3 DECODER
2.17.1 FUNCTIONAL DESCRIPTION
The interrupt controller in S5L840F receives the request from 32interrupt sources. These interrupt sources are provided by internal peripheral such as the DMA controller, UART, IIC, external interrupts, etc. The role of the interrupt controller is to ask for the FIQ or IRQ interrupt requests to the ARM940T core after the arbitration process when there are multiple interrupt requests from internal peripherals and external interrupt request pins. The arbitration process is performed by the hardware priority logic and the result is written to the interrupt pending register and users refer this register to know which interrupt has been requested.
Interrupt Sources[31:0] = {INT[27:1], |(EINT[7:3]), INT[0], EINT[2:0]} 32 Source Pending Register 32 masking logic 32 mode filter 32 Interrupt Mask Register 32 Interrupt Mode Register 32 IRQ Priority Register 32 arbiter 32 IRQ Pending Register 1 nFIQ 1 nIRQ
Interrupt Process Diagram
30-2
ICU PRELIMINARY SPECIFICATION
S5L840FX FLASH TYPE MP3 DECODER
INTERRUPT SOURCES ICU supports 28 internal interrupt sources and 8 external interrupt sources. But 5 external interrupt sources are ored to 1 source internally. Therefore, 28 internal interrupt sources, 1 ored external source and 3 external sources participate in arbitration. All interrupt sources should be high active and more than 1 cycle pulse signals. Therefore, additional logic is needed for external interrupts. Additional logic can make external interrupts change signal polarity and be distinguished from invalid sources that were generated by noise or masked by user control register.
INTERRUPT CONTROLLER OPERATION F-bit and I-bit of PSR (program status register) If the F-bit of PSR (program status register in ARM940T CPU) is set to 1, the CPU does not accept the FIQ (fast interrupt request) from the interrupt controller. If I-bit of PSR (program status register in ARM940T CPU) is set to 1, the CPU does not accept the IRQ (interrupt request) from the interrupt controller. So, to enable the interrupt reception, the F-bit or I-bit of PSR has to be cleared to 0 and also the corresponding bit of INTMSK has to be set to 1. Interrupt Mode ARM940T has 2 types of interrupt mode, FIQ or IRQ. All the interrupt sources determine the mode of interrupt to be used at interrupt request. Interrupt Pending Register S5L840F has two interrupt pending resisters. The one is source pending register(SRCPND) and the other is interrupt pending register(INTPND). These pending registers indicate whether or not an interrupt request is pending. When the interrupt sources request interrupt service the corresponding bits of SRCPND register are set to 1, at the same time the only one bit of INTPND register is set to 1 automatically after arbitration process. If interrupts are masked, the corresponding bits of SRCPND register are set to 1, but the bit of INTPND register is not changed. When a pending bit of INTPND register is set, the interrupt service routine starts whenever the I-flag or F-flag is cleared to 0. The SRCPND and INTPND registers can be read and written, so the service routine must clear the pending condition by writing a 1 to the corresponding bit in SRCPND register first and then clear the pending condition in INTPND registers with same method. Interrupt Mask Register Indicates that an interrupt has been disabled if the corresponding mask bit is 0. If an interrupt mask bit of INTMSK
30-3
ICU PRELIMINARY SPECIFICATION
S5L840FX FLASH TYPE MP3 DECODER
is 1, the interrupt will be serviced normally. If the corresponding mask bit is 0 and the interrupt is generated, the source pending bit will be set.
INTERRUPT PRIORITY GENERATING BLOCK The priority logic for 32 interrupt requests is composed of seven rotation-based arbiters: six first-level arbiters and one second-level arbiter as shown in the following figure.
ARM IRQ
ARBITER6
REQ0 REQ1 REQ2 REQ3 REQ4 REQ5
ARBITER0
REQ1/EINT0 REQ2/EINT1 REQ3/EINT2 REQ4/DBG_WAKEUP
ARBITER1
REQ0/EINTG REQ1/INT_TIMERA REQ2/INT_WDT REQ3/ Reserved REQ4/INT_TIMERC REQ5/ Reserved REQ0/INT_DMA REQ1/INT_ALARM_RTC REQ2/INT_PRI_RTC REQ3/ Reserved REQ4/INT_MIU REQ5/ Reserved REQ0/ Reserved REQ1/ Reserved REQ2/ Reserved REQ3/ Reserved REQ4/ Reserved REQ5/ Reserved REQ0/INT_UART0 REQ1/INT_SPDIF REQ2/ Reserved REQ3/INT_LCD REQ4/INT_SPI REQ5/INT_IIC REQ1/ Reserved REQ2/INT_MSTICK REQ3/INT_USB REQ4/INT_ADC
ARBITER2
ARBITER3
ARBITER4
ARBITER5
Priority Generating Block
30-4
ICU PRELIMINARY SPECIFICATION
S5L840FX FLASH TYPE MP3 DECODER
INTERRUPT PRIORITY Each arbiter can handle six interrupt requests based on the one bit arbiter mode control(ARB_MODE) and two bits of selection control signals(ARB_SEL) as follows: If ARB_SEL bits are 00b, the priority order is REQ0, REQ1, REQ2, REQ3, REQ4, and REQ5. If ARB_SEL bits are 01b, the priority order is REQ0, REQ2, REQ3, REQ4, REQ1, and REQ5. If ARB_SEL bits are 10b, the priority order is REQ0, REQ3, REQ4, REQ1, REQ2, and REQ5. If ARB_SEL bits are 11b, the priority order is REQ0, REQ4, REQ1, REQ2, REQ3, and REQ5. Note that REQ0 of an arbiter is always the highest priority, and REQ5 is the lowest one. In addition, by changing the ARB_SEL bits, we can rotate the priority of REQ1 - REQ4. Here, if ARB_MODE bit is set to 0, ARB_SEL bits are not automatically changed, thus the arbiter operates in the fixed priority mode. (Note that even in this mode, we can change the priority by manually changing the ARB_SEL bits.). On the other hand, if ARB_MODE bit is 1, ARB_SEL bits are changed in rotation fashion, e.g., if REQ1 is serviced, ARB_SEL bits are changed to 01b automatically so as to make REQ1 the lowest priority one. The detailed rule of ARB_SEL change is as follows. If REQ0 or REQ5 is serviced, ARB_SEL bits are not changed at all. If REQ1 is serviced, ARB_SEL bits are changed to 01b. If REQ2 is serviced, ARB_SEL bits are changed to 10b. If REQ3 is serviced, ARB_SEL bits are changed to 11b. If REQ4 is serviced, ARB_SEL bits are changed to 00b.
DBG OPERATION MODE
DBGACK OCCURS DURING OPERATION OF DEBUGGER UNIT IN CALMADM3. DBGACK SIGNAL MAKES THAT PENDING INTERRUPTS IS NOT PROPAGATED TO CALMADM3. IF DBGACK SIGNAL IS ACTIVE(SET TO 0), BOTH NIRQ AND NFIQ IS MASKED TO 1. DBGACK_HCLK IS SYNCHRONIZED WITH HCLK AND STOP THE WATCHDOG-TIMER OPERATION.
30-5
ICU PRELIMINARY SPECIFICATION
S5L840FX FLASH TYPE MP3 DECODER
2.17.3 REGISTER MAP
There are 9 control registers in the interrupt controller: source pending register, interrupt mode register, mask register, priority register, interrupt pending register, offset register, external interrupt polarity register, external interrupt mask register and external interrupt pending register. All the interrupt requests from the interrupt sources are first registered in the source pending register. They are divided into two groups based on the interrupt mode register, i.e., one FIQ request and the remaining IRQ requests. Arbitration process is performed for the multiple IRQ requests based on the priority register. SOURCE PENDING REGISTER (SRCPND) SRCPND register is composed of 32 bits each of which is related to an interrupt source. Each bit is set to 1 if the corresponding interrupt source generates the interrupt request and waits for the interrupt to be serviced. By reading this register, we can see the interrupt sources waiting for their requests to be serviced. Note that each bit of SRCPND register is automatically set by the interrupt sources regardless of the masking bits in the INTMASK register. In addition, it is not affected by the priority logic of interrupt controller. In the interrupt service routine for a specific interrupt source, the corresponding bit of SRCPND register has to be cleared to get the interrupt request from the same source correctly. If you return from the ISR without clearing the bit, interrupt controller operates as if another interrupt request comes in from the same source. In other words, if a specific bit of SRCPND register is set to 1, it is always considered as a valid interrupt request waiting to be serviced. The specific time to clear the corresponding bit depends on the user's requirement. The bottom line is that if you want to receive another valid request from the same source you should clear the corresponding bit first, and then enable the interrupt. You can clear a specific bit of SRCPND register by writing a data to this register. It clears only the bit positions of SRCPND corresponding to those set to one in the data. The bit positions corresponding to those that are set to 0 in the data remains as they are with no change Register SRCPND Address 0x39C0_0000 R/W R/W Description Indicates the interrupt request status. 0 = The interrupt has not been requested. 1 = The interrupt source has asserted the interrupt request. Reset Value 0x00000000
30-6
ICU PRELIMINARY SPECIFICATION
S5L840FX FLASH TYPE MP3 DECODER
SRCPND INT_ADC INT_USB INT_MSTICK Reserved INT_IIC INT_SPI INT_LCD Reserved INT_SPDIF INT_UART0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved INT_MIU Reserved INT_PRI_RTC INT_ALARM_RTC INT_DMA Reserved INT_TIMER C Reserved INT_WDT INT_TIMER A EINTG DBG_WAKEUP EINT2 EINT1 EINT0
Bit [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] 0 = Not requested, 0 = Not requested, 0 = Not requested, Not used 0 = Not requested, 0 = Not requested, 0 = Not requested, Not used 0 = Not requested, 0 = Not requested, Not used Not used Not used Not used Not used Not used Not used 0 = Not requested, Not used 0 = Not requested, Not used 0 = Not requested, Not used 0 = Not requested, Not used 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested,
Description 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested
Initial State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
INTERRUPT MODE REGISTER (INTMOD) This register is composed of 32 bits each of which is related to an interrupt source. If a specific bit is set to 1, the corresponding interrupt is processed in the FIQ (fast interrupt) mode. Otherwise, it is processed in the IRQ mode (normal interrupt). Note that at most only one interrupt source can be serviced in the FIQ mode in the interrupt controller. (You
30-7
ICU PRELIMINARY SPECIFICATION
S5L840FX FLASH TYPE MP3 DECODER
should use the FIQ mode only for the urgent interrupt.) Thus, only one bit of INTMOD can be set to 1 at most. Register INTMOD Address 0x39C0_0004 R/W R/W Description Interrupt mode register. 0 = IRQ mode 1 = FIQ mode Reset Value 0x00000000
NOTE: If an interrupt mode is set to FIQ mode in INTMOD register, FIQ interrupt will not affect INTPND and INTOFFSET registers. The INTPND and INTOFFSET registers are valid only for IRQ mode interrupt source. INTMOD INT_ADC INT_USB INT_MSTICK Reserved INT_IIC INT_SPI INT_LCD Reserved INT_SPDIF INT_UART0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved INT_MIU Reserved INT_PRI_RTC INT_ALARM_RTC INT_DMA Reserved INT_TIMER C Reserved INT_WDT INT_TIMER A EINTG DBG_WAKEUP EINT2 EINT1 EINT0 Bit [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] Description 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ Initial State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Not used
Not used
Not used Not used Not used Not used Not used Not used Not used 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 0 = IRQ, 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ 1 = FIQ Not used
Not used Not used
30-8
ICU PRELIMINARY SPECIFICATION
S5L840FX FLASH TYPE MP3 DECODER
INTERRUPT MASK REGISTER (INTMSK) Each of the 32 bits in the interrupt mask register is related to an interrupt source. If you set a specific bit to 0, the interrupt request from the corresponding interrupt source is not serviced by the CPU. (Note that even in such a case, the corresponding bit of SRCPND register is set to 1). If the mask bit is 1, the interrupt request can be serviced. Register INTMSK Address 0x39C0_0008 R/W R/W Description Determines which interrupt source is masked. The masked interrupt source will not be serviced. 1 = Interrupt service is available 0 = Interrupt service is masked Reset Value 0x00000000
INTMSK INT_ADC INT_USB INT_MSTICK Reserved INT_IIC INT_SPI INT_LCD Reserved INT_SPDIF INT_UART0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved INT_MIU Reserved INT_PRI_RTC INT_ALARM_RTC INT_DMA Reserved INT_TIMER C Reserved
Bit [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7]
Description 1 = Service available, 1 = Service available, 1 = Service available, Not used 1 = Service available, 1 = Service available, 1 = Service available, Not used 1 = Service available, 1 = Service available, Not used Not used Not used Not used Not used Not used Not used 1 = Service available, Not used 1 = Service available, 1 = Service available, 1 = Service available, Not used 1 = Service available, Not used 0 = Masked 0 = Masked 0 = Masked 0 = Masked 0 = Masked 0 = Masked 0 = Masked 0 = Masked 0 = Masked 0 = Masked 0 = Masked 0 = Masked 0 = Masked
Initial State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
30-9
ICU PRELIMINARY SPECIFICATION
S5L840FX FLASH TYPE MP3 DECODER
INT_WDT INT_TIMER A EINTG DBG_WAKEUP EINT2 EINT1 EINT0
[6] [5] [4] [3] [2] [1] [0]
1 = Service available, 1 = Service available, 1 = Service available, 1 = Service available, 1 = Service available, 1 = Service available, 1 = Service available,
0 = Masked 0 = Masked 0 = Masked 0 = Masked 0 = Masked 0 = Masked 0 = Masked
0 0 0 1 0 0 0
PRIORITY REGISTER (PRIORITY) Register PRIORITY Address 0x39C0_000C R/W W Description IRQ priority control register Reset Value 0x7f
PRIORITY ARB_SEL6
Bit [20:19] Arbiter 6 group priority order set 00 = REQ 0-1-2-3-4-5 10 = REQ 0-3-4-1-2-5
Description 01 = REQ 0-2-3-4-1-5 11 = REQ 0-4-1-2-3-5
Initial State 0
ARB_SEL5
[18:17]
Arbiter 5 group priority order set 00 = REQ 1-2-3-4 01 = REQ 2-3-4-1 10 = REQ 3-4-1-2 11 = REQ 4-1-2-3 Arbiter 4 group priority order set 00 = REQ 0-1-2-3-4-5 10 = REQ 0-3-4-1-2-5 Arbiter 3 group priority order set 00 = REQ 0-1-2-3-4-5 10 = REQ 0-3-4-1-2-5 Arbiter 2 group priority order set 00 = REQ 0-1-2-3-4-5 10 = REQ 0-3-4-1-2-5 Arbiter 1 group priority order set 00 = REQ 0-1-2-3-4-5 10 = REQ 0-3-4-1-2-5 01 = REQ 0-2-3-4-1-5 11 = REQ 0-4-1-2-3-5
0
ARB_SEL4
[16:15]
0
ARB_SEL3
[14:13]
0 01 = REQ 0-2-3-4-1-5 11 = REQ 0-4-1-2-3-5 0 01 = REQ 0-2-3-4-1-5 11 = REQ 0-4-1-2-3-5 0 01 = REQ 0-2-3-4-1-5 11 = REQ 0-4-1-2-3-5 0
ARB_SEL2
[12:11]
ARB_SEL1
[10:9]
ARB_SEL0
[8:7]
Arbiter 0 group priority order set 00 = REQ 1-2-3-4 01 = REQ 2-3-4-1 10 = REQ 3-4-1-2 11 = REQ 4-1-2-3 Arbiter 6 group priority rotate enable 0 = Priority does not rotate, 1 = Priority rotate enable Arbiter 5 group priority rotate enable 0 = Priority does not rotate, 1 = Priority rotate enable Arbiter 4 group priority rotate enable 0 = Priority does not rotate, 1 = Priority rotate enable Arbiter 3 group priority rotate enable 0 = Priority does not rotate, 1 = Priority rotate enable
ARB_MODE6 ARB_MODE5 ARB_MODE4 ARB_MODE3
[6] [5] [4] [3]
1 1 1 1
30-10
ICU PRELIMINARY SPECIFICATION
S5L840FX FLASH TYPE MP3 DECODER
ARB_MODE2 ARB_MODE1 ARB_MODE0
[2] [1] [0]
Arbiter 2 group priority rotate enable 0 = Priority does not rotate, 1 = Priority rotate enable Arbiter 1 group priority rotate enable 0 = Priority does not rotate, 1 = Priority rotate enable Arbiter 0 group priority rotate enable 0 = Priority does not rotate, 1 = Priority rotate enable
1 1 1
INTERRUPT PENDING REGISTER (INTPND) Each of the 32 bits in the interrupt pending register shows whether the corresponding interrupt request is the highest priority one that is unmasked and waits for the interrupt to be serviced. Since INTPND is located after the priority logic, only one bit can be set to 1 at most, and that is the very interrupt request generating IRQ to CPU. In interrupt service routine for IRQ, you can read this register to determine the interrupt source to be serviced among 32 sources. Like the SRCPND, this register has to be cleared in the interrupt service routine after clearing SRCPND register. We can clear a specific bit of INTPND register by writing a data to this register. It clears only the bit positions of INTPND corresponding to those set to one in the data. The bit positions corresponding to those that are set to 0 in the data remains as they are with no change. Register INTPND Address 0x39C0_0010 R/W R/W Description Indicates the interrupt request status. 0 = The interrupt has not been requested 1 = The interrupt source has asserted the interrupt request
NOTE: If the FIQ mode interrupt is occurred, the corresponding bit of INTPND will not be turned on. Because the INTPND register is available only for IRQ mode interrupt. INTPND INT_ADC INT_USB INT_MSTICK Reserved INT_IIC INT_SPI INT_LCD Reserved INT_SPDIF Bit [31] [30] [29] [28] [27] [26] [25] [24] [23] 0 = Not requested, 0 = Not requested, 0 = Not requested, Not used 0 = Not requested, 0 = Not requested, 0 = Not requested, Not used 0 = Not requested, 1 = Requested 1 = Requested 1 = Requested 1 = Requested Description 1 = Requested 1 = Requested 1 = Requested Initial State 0 0 0 0 0 0 0 0 0
Reset Value 0x00000000
30-11
ICU PRELIMINARY SPECIFICATION
S5L840FX FLASH TYPE MP3 DECODER
INT_UART0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved INT_MIU Reserved INT_PRI_RTC INT_ALARM_RTC INT_DMA Reserved INT_TIMER C Reserved INT_WDT INT_TIMER A EINTG DBG_WAKEUP EINT2 EINT1 EINT0
[22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
0 = Not requested, Not used Not used Not used Not used Not used Not used Not used 0 = Not requested, Not used 0 = Not requested, 0 = Not requested, 0 = Not requested, Not used 0 = Not requested, Not used 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested, 0 = Not requested,
1 = Requested
0 0 0 0 0 0 0 0
1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested 1 = Requested
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
INTERRUPT OFFSET REGISTER (INTOFFSET) The number in the interrupt offset register shows which interrupt request of IRQ mode is in the INTPND register. This bit can be cleared automatically by clearing SRCPND and INTPND. Register INTOFFSET Address 0x39C0_0014 R/W R Description Indicates the IRQ interrupt request source Reset Value 0x00000000
INT Source INT_ADC INT_USB INT_MSTICK Reserved INT_IIC INT_SPI INT_LCD
The OFFSET value 31 30 29 28 27 26 25 INT_MIU
INT Source Reserved Reserved INT_PRI_RTC INT_ALARM_RTC INT_DMA Reserved
The OFFSET value 15 14 13 12 11 10 9
30-12
ICU PRELIMINARY SPECIFICATION
S5L840FX FLASH TYPE MP3 DECODER
Reserved INT_SPDIF INT_UART0 Reserved Reserved Reserved Reserved Reserved Reserved
24 23 22 21 20 19 18 17 16
INT_TIMER C Reserved INT_WDT INT_TIMER A EINTG DBG_WAKEUP EINT2 EINT1 EINT0
8 7 6 5 4 3 2 1 0
NOTE: If the FIQ mode interrupt is occurred, the INTOFFSET will not be affected. Because the INTOFFSET register is available only for IRQ mode interrupt.
EXTERNAL INTERRUPT POLARITY SELECTION REGISTER Register EINTPOL Address 0x39C0_0018 R/W R/W Description Indicates external interrupt polarity Reset Value 0x00000000
INTPND External Interrupt 7 External Interrupt 6 External Interrupt 5 External Interrupt 4 External Interrupt 3 External Interrupt 2 External Interrupt 1 External Interrupt 0
Bit [7] [6] [5] [4] [3] [2] [1] [0]
Description 0 = Falling edge interrupt, 1 = Rising edge interrupt 0 = Falling edge interrupt, 1 = Rising edge interrupt 0 = Falling edge interrupt, 1 = Rising edge interrupt 0 = Falling edge interrupt, 1 = Rising edge interrupt 0 = Falling edge interrupt, 1 = Rising edge interrupt 0 = Falling edge interrupt, 1 = Rising edge interrupt 0 = Falling edge interrupt, 1 = Rising edge interrupt 0 = Falling edge interrupt, 1 = Rising edge interrupt
Initial State 0 0 0 0 0 0 0 0
EXTERNAL INTERRUPT PENDING REGISTER Register EINTPEND Address 0x39C0_001C R/W R/W Description Indicates whether external interrupts are pending. Reset Value 0x00000000
INTPND External Interrupt 7
Bit [7]
Description 0 = No interrupt request pending, 1 = Interrupt request pending
Initial State 0
30-13
ICU PRELIMINARY SPECIFICATION
S5L840FX FLASH TYPE MP3 DECODER
External Interrupt 6 External Interrupt 5 External Interrupt 4 External Interrupt 3 Reserved Reserved Reserved
[6] [5] [4] [3] [2] [1] [0]
0 = No interrupt request pending, 1 = Interrupt request pending 0 = No interrupt request pending, 1 = Interrupt request pending 0 = No interrupt request pending, 1 = Interrupt request pending 0 = No interrupt request pending, 1 = Interrupt request pending Not used Not used Not used
0 0 0 0 0 0 0
EXTERNAL INTERRUPT MASK REGISTER Register EINTMSK Address 0x39C0_0020 R/W R/W Description Indicates whether external interrupts are masked Reset Value 0x00000000
INTPND External Interrupt 7 External Interrupt 6 External Interrupt 5 External Interrupt 4 External Interrupt 3 External Interrupt 2 External Interrupt 1 External Interrupt 0
Bit [7] [6] [5] [4] [3] [2] [1] [0]
Description 0 = External interrupt disable 1 = External interrupt enable 0 = External interrupt disable 1 = External interrupt enable 0 = External interrupt disable 1 = External interrupt enable 0 = External interrupt disable 1 = External interrupt enable 0 = External interrupt disable 1 = External interrupt enable 0 = External interrupt disable 1 = External interrupt enable 0 = External interrupt disable 1 = External interrupt enable 0 = External interrupt disable 1 = External interrupt enable
Initial State 0 0 0 0 0 0 0 0
30-14
MIU PRELIMINARY SPECIFICATION REV0.0
S5L840FX FLASH TYPE MP3 DECODER
MIU (Memory Interface Unit)
User's mamual
REV0.0
Kim, Hye-ryeong MEDIA Plyer P/J System LSI Business Device Solution Network Division Samsung Electronics
March 28, 2003
1/8
MIU PRELIMINARY SPECIFICATION REV0.0
S5L840FX FLASH TYPE MP3 DECODER
2.16.1 FUNCTIONAL DESCRIPTION
Features MIU supports ROM interface, SRAM interfaces and NOR FLASH memory device interfaces. Main features of MIU are as followings. supports 1 ROM access areas and 1 SRAM access areas. Each ROM and SRAM access areas have 32Mbyte address space respectively. supports 8/16/32bit access to SRAM and ROM. supports 4Mbit(512Kbyte) NOR flash memory. Supports 8/16/32bit access in NOR flash memory READ operation. But, only 32bit access is allowed in WRITE operation. not supports burst mode. Only single transfer is supported.
Memory configuration of S5L840FX
shows overall address configuration in S5L840FX.
shows memory mapped IO configuration of SFRS area in S5L840FX.
March 28, 2003
2/8
MIU PRELIMINARY SPECIFICATION REV0.0
S5L840FX FLASH TYPE MP3 DECODER
: physical memory area
0xFFFF_FFFF 0x3FFF_FFFF
SFRS(AHB/APB)
0x3800_0000
reserved area3 reserved area
0xC000_0000 0xBFFF_FFFF 0x3000_0000 0x2E00_0000 0x2C00_0000 0x2801_8000 0x2800_0000 0x2408_0000 0x2400_0000 0x2000_1000 0x2000_0000 0x1FFF_FFFF
reserved area2
0x8000_0000 0x7FFF_FFFF
reserved area reserved area reserved area SRAM (96K) reserved area NOR FLASH (512K) reserved area Boot ROM (4K)
reserved area1
0x4000_0000 0x3FFF_FFFF
reserved area available area
0x0000_0000
0x0000_0000
Overall Address Configuration
March 28, 2003
3/8
MIU PRELIMINARY SPECIFICATION REV0.0
S5L840FX FLASH TYPE MP3 DECODER
0x3FFF_FFFF
0x3FFF_FFFF
SFRS (APB) 64M
Unused
SFRS (APB)
reserved
0x3C00_0000 0x3BFF_FFFF
reserved ICU
0x39E0_0000 0x39C0_0000
0x3C00_0000 0x3BFF_FFFF
SFRS (AHB) 64M
reserved
SFRS (AHB)
0x3800_0000
IO DMA MIU ADM
0x3840_0000 0x3820_0000 0x3800_0000
0x3800_0000
USB IIS out GPIO ADC SPI UART SPDIF IIS in IIC WDT Timer Mem Stick Clock_Gen SD Card MM Card SM Card LCD I/F APB bridge
0x3D10_0000 0x3D00_0000 0x3CF0_0000 0x3CE0_0000 0x3CD0_0000 0x3CC0_0000 0x3CB0_0000 0x3CA0_0000 0x3C90_0000 0x3C80_0000 0x3C70_0000 0x3C60_0000 0x3C50_0000 0x3C40_0000 0x3C30_0000 0x3C20_0000 0x3C10_0000 0x3C00_0000
Memory Mapped IO Configuration
March 28, 2003
4/8
MIU PRELIMINARY SPECIFICATION REV0.0
S5L840FX FLASH TYPE MP3 DECODER
SRAM/ROM controller Register map
Static(ROM/SRAM) memory access parameter registers Register MIURPARA MIUSPARA Address 14~17H 18~1BH R/W R/W R/W Description ROM parameter register SRAM parameter register Width 32 bits 32 bits
Bits [31:24] [23:20] [19:16] [15:8] TACS TCOS TACC
Field
Description Don't use. These bits appear as zero when read. Address set-up time before chip select Chip select set-up time before output enable Access cycles. This field must not be zero. Otherwise, the result of access is unpredictable.
Reset value 1h 1h 03h
[7:4] [3:0]
TOCH TCAH
Chip select hold time after output enable Address hold time after chip select
1h 1h
* Recommend : TCOS, TOCH cycle is recommended to keep up more than one cycle time. Otherwise, It makes a problem at memory read cycle if you adopt a synchronous SRAM. *The Unit of MIURPARA and MIUSPARA fields is clock cycle.
CK ADR
CSN
TACS TCAH
OEN/WEN
TCOS TACC TOCH
Parameter Diagram
March 28, 2003
5/8
MIU PRELIMINARY SPECIFICATION REV0.0
S5L840FX FLASH TYPE MP3 DECODER
Static(ROM/SRAM) memory size parameter registers Register MIUSSIZE Address 1C~1FH R/W W Description Static memory size pre-setting Width 32 bits
Bits [31:24] [23:16] [15:8] [7:0] SIZE3 SIZE2 SIZE1 SIZE0
Field
Description Static memory 3 size (reserved in S5L840FX) Static memory 2 size (SRAM area in S5L840FX) Static memory 1 size (NOR FLASH in S5L840FX) Static memory 0 size (ROM in S5L840FX)
Reset value 00h 80h 40h 01h
Parameter 1step equals 4Kbyte of memory size. 00h = reserved 01h = 4Kbyte size. ............ 10h = 64Kbyte size ............ 80h = 512Kbyte size. memory size 4Kbyte , 3Kbyte 4Kbyte .
Access Parameter
SRAM/ROM controller, access cycle time parameter set.
CK ADR
CSN
TACS TCAH
OEN/WEN
TCOS TACC TOCH
March 28, 2003
6/8
MIU PRELIMINARY SPECIFICATION REV0.0
S5L840FX FLASH TYPE MP3 DECODER
If you use synchronous SRAM using the clock which same phase frequency with HCLK, you must keep up the TACC and TOCH for more than one cycle time.
Minimum data phase cycle time of SRAM/ROM controller is 2cycle. First 1cycle is `Chip select setup cycle time' and second 1cycle is `Access cycle time'. MIURPARA/MIUSPARA 32'h0001_0100. 2cycle access read F/F bus . 2cycle access . Parameter 32'h0001_0110(minimum value) F/F bus access 3cycle . access parameter setting assemble . Example. Access time parameter setting (3cycle access)
ld A8, #rMIUBASE
//minimum cycle time parameter ld ld ldw ldw ldw ldw R0, #0001h R1, #0110h @[A8+rMIUSPARA_H], R0 @[A8+rMIUSPARA_L], R1 //SRAM PARAMETER SET @[A8+rMIURPARA_H], R0 @[A8+rMIURPARA_L], R1 //ROM PARAMETER SET.
March 28, 2003
7/8
MIU PRELIMINARY SPECIFICATION REV0.0
S5L840FX FLASH TYPE MP3 DECODER
Size parameter & Interrupt
:
0x3FFF_FFFF
S5L840FX physical memory area
SFRS(AHB/APB)
0x3800_0000 0x3000_0000
reserved area
0x3000_0000 0x2C00_0000 0x2801_8000 0x2800_0000 0x2408_0000 0x2400_0000 0x2000_1000 0x2000_0000 0 x1FFF_FFFF
reserved area out of range
0x2C00_0000
512KB
reserved area reserved area SRAM (76K) reserved area NOR FLASH (256K) reserved area Boot ROM (4K)
reserved area out of range
0x2801_8000 0x2800_0000
512KB
0x2408_0000 0x2400_0000
SRAM (76K) reserved area out of range NOR FLASH (256K) reserved area out of range Boot ROM
(4K)
512KB
0x2000_1000 0x2000_0000
512KB
reserved area
0x0000_0000
S5L840FX out-of-range interrupt diagram from MIU MIU out-of-range signal 4 SRAM-like . user MIUSSIZE access toggle. SRAM-like size register 8 , MIUSSIZE out-of-range address register
. maximum address size 8'h80(512KByte) MIUSSIZE write . MIUSSIZE register write 32bit update . reset MIUSSZE default 32'h0080_8001.
March 28, 2003
8/8
S5L840F (Preliminary Spec)
IODMA
9
IODMA CONTROLLER
OVERVIEW
S5L840F supports four-channel IODMA (I/O Direct Memory Access) controller that performs data transfer without core intervention. Each channel of DMA controller has two data transfer directions, which are memory-to-IO and IO-to-memory. In other words, each channel can handle the following data transfers: 1. source is in the system bus (AHB) while destination is in the peripheral bus (APB) (ex, memory to an I/O device transfer) 2. source is in the peripheral bus (APB) while destination is in the system bus (AHB) (ex, an I/O device to memory transfer) In IODMA, DMA is made of repetition of read-and-write and this read-and-write is atomic and is called as a single transfer. A single transfer is a minimum indivisible unit of DMA's. The DMA operation can be requested by either software or hardware including external DMA source.
8-1
IODMA
S5L840F (Preliminary Spec)
SINGLE TRANSFER PROTOCOL
There are 2 signals for DMA protocol between IODMA controller and an IO peripheral. Signal Name DMA_REQ_n DMA_ACK_n In/Out In Out Description Low-active single transfer request signal. Low-active single transfer acknowledge signal.
The following FSM(Finite State Machine) is a recommended FSM for IO peripheral supporting for IODMA.
IDLE (need of ST) ~(need of ST) & ACKn
State IDLE REQ TRANS
REQn 1'b1 1'b0 1'b1
(need of ST) & ACKn REQ ~ACKn TRANS ST : Single transfer
ACKn
~ACKn
Figure 9-1. FSM for IODMA IDLE. REQ. As an initial state, it waits for the DMA request. If it comes, go to REQ state. At this state, DMA_ACK_n and DMA_REQ_n are high. In this state, DMA_REQ_n becomes low and wait for DMA_ACK_n signal asserted.
TRANS. In this state, the IODMA executes just one single transfer. IODMA can execute only one single transfer of 4 channels at one moment. Therefore, arbitration among channels is needed and this arbitration is executed before a single transfer is started. In arbitration, a channel with higher priority will acquire an ownership of IODMA for its single transfer. The priority of each channel is fixed. Channel 0 has the highest priority and Channel 3 has the lowest priority.
9-2
S5L840F (Preliminary Spec)
IODMA
minimum 6 cycles HCLK CH0_REQn CH0_ACKn
inter-channel arbitration
AHB+ read
AHB+ write
a single transfer for channel0
HCLK CH0_REQn CH1_REQn CH0_ACKn CH1_ACKn
inter-channel arbitration
AHB+ read
AHB+ write
inter-channel arbitration
AHB+ read
AHB+ write
a single transfer for channel0
a single transfer for channel1
Figure 9-2. Single Data Transfer Timing
9-3
IODMA
S5L840F (Preliminary Spec)
IODMA SPECIAL REGISTERS
BASE ADDRESS REGISTERS FOR EACH CHANNEL Register DMABASE0 DMABASE1 DMABASE2 DMABASE3 Address 38400000H 38400020H 38400040H 38400060H R/W R/W R/W R/W R/W Description Base address register for channel 0 Base address register for channel 1 Base address register for channel 2 Base address register for channel 3 Width 32 bits 32 bits 32 bits 32 bits
Bits [31:0]
Field BA[31:0]
Description This field is memory base address for DMA and is represented in byte addressing with 32bits. This address should be aligned to a data size of a single transfer.
Reset Value 00000000h
TRANSFER COUNT REGISTERS FOR EACH CHANNEL Register DMATCNT0 DMATCNT1 DMATCNT2 DMATCNT3 Address 38400008H 38400028H 38400048H 38400068H R/W R/W R/W R/W R/W Description Transfer count register for channel 0 Transfer count register for channel 1 Transfer count register for channel 2 Transfer count register for channel 3 Width 32 bits 32 bits 32 bits 32 bits
Bits [31:20] [19:0]
Field TCNT[19:0]
Description This field is reserved and appears as zero when read. This field is total number of single transfers.
Reset Value - XXXXXh
9-4
S5L840F (Preliminary Spec)
IODMA
CURRENT MEMORY ACCESS ADDRESS REGISTERS FOR EACH CHANNEL Register DMACADDR0 DMACADDR1 DMACADDR2 DMACADDR3 Address 3840000CH 3840002CH 3840004CH 3840006CH R/W R R R R Description Current memory address register for channel 0 Current memory address register for channel 1 Current memory address register for channel 2 Current memory address register for channel 3 Width 32 bits 32 bits 32 bits 32 bits
Bits [31:0]
Field
Description
Reset Value XXXXXXXXh
CADDR[31:0] This field is a current memory access address of DMA and is represented in byte addressing with 32bits.
CONFIGURATION REGISTERS FOR EACH CHANNEL Register DMACON0 DMACON1 DMACON2 DMACON3 Address 38400004H 38400024H 38400044H 38400064H R/W R/W R/W R/W R/W Description Configuration register for channel 0 Configuration register for channel 1 Configuration register for channel 2 Configuration register for channel 3 Width 32 bits 32 bits 32 bits 32 bits
Bits [31:30]
Field DEVSEL[1:0] Device selection.
Ch 0 1 2 3 Sel 00 IIS out LCD IIS in SPDIF 01
Description
10 LCD MS SPI in SPI out 11 UART0 out SDC LCD LCD
Reset Value XXb
USB Ch1 SM USB Ch2 USB Ch3
[29] [28]
DIR ADDRCON
DMA direction 0 : IO to Memory DMA, 1 : Memory to IO DMA Memory address control bit. This bit has to be "0" This field indicates how to determine memory access address for next single transfer.
0 Normal mode. The relationship of next memory access address (NADDR) with current memory access address (CADDR) is NADDR = CADDR + 1 * size_of(ST3).
Xb Xb
9-5
IODMA
S5L840F (Preliminary Spec)
(Continued) 0X2047_0000 Bits [27:24] Field SCHCNT[3:0] Sub-channel count. Note that channel0, channel 1, channel 2 and channel 3 should have 0 or 1 in this field. In other words, channel 1, channel 2 and channel 3 cannot have more than 2 sub-channels. Otherwise, the result is unpredictable. [23:22] [21:19] DSIZE[1:0] BLEN[2:0] Data size. 00 : byte, 01 : half word, 10 : word, 11 : reserved Burst length (BL). 000 : (BL = 1), 001 : (BL = 2), 010 : (BL = 3), 011 : (BL = 4), 100 : (BL = 5), 101 : (BL = 6), 110 : (BL = 7), 111 : (BL = 8) [18] RELOAD Reload enable. If "1", after whole completion of DMA, channel controller automatically restart the same DMA without commands. [17] HCOMINT Half completion interrupt enable. If "1", channel controller make interrupt to inform core on half completion of DMA. This is used for double buffering. Half completion is checked with following inequality. (DMASTATx[19:0] >= DMATCNTx[19:1]) [16] WCOMINT Whole completion interrupt enable. If "1", channel controller inform core on the completion of DMA by interrupt. [15:0] OFFSET[15:0] Offset value. This field is used to calculating next memory access address in subchannel mode. XXXXh Xb Xb Xb XXXb XXb Description Reset Value XXXXb
9-6
S5L840F (Preliminary Spec)
IODMA
CURRENT TRANSFER COUNT REGISTERS FOR EACH CHANNEL Register DMACTCNT0 DMACTCNT1 DMACTCNT2 DMACTCNT3 Address 38400010H 38400030H 38400050H 38400070H R/W R R R R Description Current transfer count register for channel 0 Current transfer count register for channel 1 Current transfer count register for channel 2 Current transfer count register for channel 3 Width 32 bits 32 bits 32 bits 32 bits
Bits [31:20] [19:0]
Field - CTCNT[19:0]
Description This field is reserved and appears as zero when read. This field shows the number of single transfer to be remained for whole DMA transfer.
Reset Value - XXXXXh
NOTE: Normally, Completion of single transfer decreases CTCNT by 1.
CHANNEL COMMAND REGISTERS Register DMACOM0 DMACOM1 DMACOM2 DMACOM3 Address 38400014H 38400034H 38400054H 38400074H R/W W W W W Description Channel 0 command register Channel 1 command register Channel 2 command register Channel 3 command register Width 32 bits 32 bits 32 bits 32 bits
Bits [31:3] [2:0]
Field - COM[2:0]
Description This field is reserved and appears as zero when read. 000 - 001 : No operation 010 : HOLD command 011 : SKIP command * HOLD command and SKIP command is only for channel 0. Other channels consider these commands as no operations. 100 : DMA channel on 101 : DMA channel off 110 : clear half completion state bit 111 : clear whole completion state bit and half completion state bit.
Reset Value - 000b
9-7
IODMA
S5L840F (Preliminary Spec)
CHANNEL 0 OFFSET2 REGISTER Register DMANOFF0 Address 38400018H R/W R/W Description Channel 0 offset2 register Width 32 bits
Bits [31:16] [15:0]
Field - OFF2CH0[15:0]
Description This field is reserved and appears as zero when read. Offset2 value. This field is used for calculating next memory access address in Multi-subchannel mode.(Not Used)
Reset Value - XXXXh
NOTE: This register is for channel 0 and the other channels do not have offset2 register.
ALL CHANNEL STATUS REGISTER Register DMAALLST Address 38400100H R/W R Description All channel status register Width 32 bits
Bits [31:15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3]
Field - DMABUSY3 HCOM3 WCOM3 - DMABUSY2 HCOM2 WCOM2 - DMABUSY1 HCOM1 WCOM1 HOLD_SKIP Channel 0 Channel 1 Channel 2 Channel 3
Description This field is reserved and appears as zero when read. DMA busy. Half completion. Whole completion. This field is reserved and appears as zero when read. DMA busy. Half completion. Whole completion. This field is reserved and appears as zero when read. DMA busy. Half completion. Whole completion. When 1, this field indicates that HOLD or SKIP command is executing and is not completed. DMA busy. Half completion. Whole completion.
Reset value - 0b 0b 0b - 0b 0b 0b - 0b 0b 0b 0b
[2] [1] [0]
DMABUSY0 HCOM0 WCOM0
0b 0b 0b
NOTE: This register is for observing all DMA channels by just a single word read.
9-8
Chapter 10. WDT module
Watchdog timer does two main functions: watchdog function and start signal generation after main clock oscillation stabilization. Watchdog function is for a situation where the system goes to in abnormal state. In this situation, if the system cannot clear the counter in the watchdog timer, the counter will count up to overflow and generate a reset signal to initialize all the system. So normal system should periodically clear the counter in the watchdog timer. The second function of the watchdog timer is oscillation stabilization. When the system power is on, the main clock from the PLL is not stable signal. So the system should wait until this main clock is stabilized. Waiting for an enough time to stabilize the main clock, watchdog timer generates the start signal that will start all the system.
FEATURES
Periodic interrupt generation Global reset generation by watchdog timer Start signal generation for oscillation stabilization 8-bits enable/disable register
BLOCK DIAGRAM
Watchdog timer consists of internal clock divider, pre-scaler and internal counter. The clock divider divides the main clock with pre-defined divisors which are 2048, 1024, 256, and 128. The divided clocks are selected by the WDT_CS flag in the control register and pre-scaled again by 4bits pre-scaler. The clock generated from the pre-scaler is supported to the internal 11-bits counter that will generate start signal, reset signal, and interrupt signal.
HCLK_PRE one cycle clock divider PCLK PCLK / 2048 PCLK / 1024 PCLK / 256 PCLK / 128 count clock after 64 count clocks 11-bits Counter (WDT_CNT) after 128 count clocks WDT_CS HCLK_PRE WDT_INT_EN WDT_EN after 2048 count clocks one cycle RESET START_HCLK
MUX
4-bits WDT_PRE
WDT_INT
Figure 1. Watch-dog timer block diagram
S5L840F
Watchdog Timer
PIN DESCRIPTION
Pin Name clk reset_n APB Interface psel penable pwrite paddr pwdata prdata Control Signals st_mode wdt_stop wdt_int wdt_start wdt_reset wdt_fast wdt_noreset wdt_start_hclk Width 1 1 1 1 1 3 32 32 1 1 1 1 1 1 1 1 I/O I I I I I I I O I I O O O I I O Global clock Global reset Selection in APB Enable in APB Write/Read in APB Address in APB Write data in APB Read data in APB Scan test mode Stop the function of the watchdog timer Basic timer interrupt Basic timer start signal for oscillation stabilization Watch-dog timer reset signal Simulation option signal for wdt output signals Simulation option signal for disabling wdt_reset Hclk one cycle signal of wdt_start Description
clk Main clock. The clock after the power-on is 27 MHz directed from the PLL. In normal operation, APB clock is supported. reset_n Global reset to reset the internal register APB interface signals (psel, penable, pwrite, paddr, pwdata, prdata) AMBA APB interface signals st_mode Scan test mode signal. In scan test mode, the internally generated or gated clocks are disabled and the main clock is used for all the internal flip-flops. This signal is used the selection signal for the clock muxing. wdt_stop Watchdog timer stop signal. In debugging mode, the watchdog timer should not operate as normal. The wdt_stop signal is used to temporarily stop the watchdog timer function. wdt_int Watchdog timer interrupt signal. When the interrupt operation is enabled, the interrupt signal is generated periodically. The time can be adjusted by the WDT_CS and WDT_PRE values. wdt_start Start signal. This signal will be long enough to stabilize the clock from the PLL after the power-on. After the stabilization of the clock, the reset signals of all the other modules are released and they start the normal operation. wdt_reset
2
S5L840F
Watchdog Timer
When the chip goes into abnormal state, it will not execute the normal operation. In this case, the normal clear operation for the watchdog timer may not be executed. When the watchdog timer is not cleared periodically, the reset signal is generated that will reset all the chip to go into the power-on state. wdt_fast For fast simulation, it makes wdt_start, wdt_int, wdt_reset to be generated at more short time than normal operations. wdt_noreset For long time simulation, it sets wdt global reset(wdt_reset) to zero wdt_start_hclk This signal is hclk_pre one cycle signal of wdt_start.
REGISTERS
Name WDTCON WDTCNT WDTCON Name WDTCON 31 15 30 14 Width 32 29 28 Address R/W 0x3c80 0000(0x39 0000) R/W 27 11 26 25 24 23 7 Description Control Register 22 6 21 5 20 19 Reset 0x0000 0000 18 17 WDT_PRE 2 1 16 0 Width 32 32 Address(Virtual) R/W 0x3c80 0000(0x39 0000) R/W 0x3c80 0000(0x39 0004) R/W Description Control Register 11-bits internal counter Reset 0x0000 0000 0x0000 0000
13 12 WDT_CS Name WDT_PRE
10 9 8 WDT_CLR
4 3 WDT_EN
Bits 19:16 15
WDT_INT_EN
14:12
WDT_CS
11:8
WDT_CLR
7:0
WDT_EN
Type Description R/W Pre-scale value Enable or disable the periodic interrupt generation when watchdog timer is enabled. R/W 0 Disable the periodic interrupt generation 1 Enable the periodic interrupt generation Clock selection 3'b100 PCLK / 2048 3'b001 PCLK / 1024 R/W 3'b010 PCLK / 256 3'b011 PCLK / 128 3'b000 PCLK / 8 Clear the internal 11-bits counter register. As this field is write-only, the read value is always zero. W 4'b1010 Clear the internal 11-bits counter register Others Nothing Enable the watch-dog timer 8'b10100101 Disable the reset/start signal generation R/W by the watchdog timer. Others Nothing
3
S5L840F
WDTCNT Name WDTCNT 31 15 30 14 Width 32 29 13 28 12 Address R/W 0x3c80 0000(0x39 0004) R 27 11 26 10 25 9 Type R 24 8 23 7
Watchdog Timer
Description 11-bits internal counter 22 6 21 20 19 3 18 2
Reset 0x0000 0000 17 1 16 0
5 4 WDT_CNT
Bits 10:0
Name WDT_CNT
Description 11-bits internal counter
4
S5L840F
Watchdog Timer
PRESCALING
System clock is scaled in two stages: WDT_PRE and WDT_CS. The WDT_CS has 8 types of prescale value and the WDT_PRE has a 4-bits resolution for pre-scaling. When the power is on, the clock generated from the PLL is not clean signal that should not be used for the operation of the chip. It takes 3 ~ 4 ms to stabilize the PLL. The watchdog timer in S5L840F waits for 4.85 ms after its reset is released. The start signal will trigger the release of the all the other reset signals when the clock from the PLL is stabilized enough. When the watchdog timer interrupt is enabled, periodic interrupt signal is generated that will be used to clear the watchdog counter. When the chip falls to abnormal state, it should be reset. When the watchdog timer is not cleared and counts up to overflow, it generates the reset signal and reset the chip. The time is defined by the WDT_CS and WDT_PRE as shown in table 1, table 2, table 3 and table4.
Frequency/ Period WDT_PRE = 0 Frequency/ Period WDT_START (x64) Frequency/ Period WDT_INT (x128) Frequency/ Period WDT_RESET (x2048) Frequency/ Period
WDT_CS
13.18 KHz 13.18 KHz 0.21 KHz 0.10 KHz 6.44 Hz 75.85 us 75.85 us 4.85 ms 9.71 ms 155.34 ms 26.37 KHz 26.37 KHz 0.41 KHz 0.21 KHz 12.87 Hz PCLK / 1024 37.93 us 37.93 us 2.43 ms 4.85 ms 77.67 ms 105.47 KHz 105.47 KHz 1.65 KHz 0.82 KHz 51.50 Hz PCLK / 256 9.48 us 9.48 us 0.61 ms 1.21 ms 19.42 ms 210.94 KHz 210.94 KHz 3.30 KHz 1.65 KHz 103.00 Hz PCLK / 128 4.74 us 4.74 us 0.30 ms 0.61 ms 9.71 ms 3.375MHz 3,375MHz 52,73KHz 26,37KHz 1,65KHz PCLK / 8 296.3 ms 296.3ms 18.96us 37.93us 606.81us Table 1. Pre-scaled clock frequency and periods when WDT_PRE = 0 and PCLK = 27 MHz
PCLK / 2048 Frequency/ Period WDT_PRE = 15 Frequency/ Period WDT_START (x64) Frequency/ Period WDT_INT (x128) Frequency/ Period WDT_RESET (x2048) Frequency/ Period
WDT_CS
13.18 KHz 0.82 KHz 12.87 KHz 6.44 KHz 0.40 Hz 75.85 us 1,213.63 us 77.67 ms 155.34 ms 2,485.51 ms 26.37 KHz 1.65 KHz 25.75 KHz 12.87 KHz 0.80 Hz PCLK / 1024 37.93 us 606.81 us 38.84 ms 77.67 ms 1,242.76 ms 105.47 KHz 6.59 KHz 103.00 KHz 51.50 KHz 3.22 Hz PCLK / 256 9.48 us 151.70 us 9.71 ms 19.42 ms 310.69 ms 210.94 KHz 13.18 KHz 205.99 KHz 103.00 KHz 6.44 Hz PCLK / 128 4.74 us 75.85 us 4.85 ms 9.71 ms 155.34 ms 3.375MHz 0.21MHz 3.296KHz 1.648KHz 102.99Hz PCLK / 8 296.3 ms 5.037us 322.37us 644.74us 10.3ms Table 2. Pre-scaled clock frequency and periods when WDT_PRE = 15 and PCLK = 27 MHz
PCLK / 2048
5
S5L840F
WDT_START (x64) Frequency/ Period
Watchdog Timer
WDT_INT (x128) Frequency/ Period WDT_RESET (x2048) Frequency/ Period
WDT_CS
Frequency/ Period
WDT_PRE = 0 Frequency/ Period
0.25 Hz 0.125 Hz 0.00781Hz 4s 8s 128s 0.5Hz 0.25 Hz 0.0156Hz PCLK / 1024 2s 4s 64s 2Hz 1Hz 0.0625Hz PCLK / 256 0.5s 1s 16s 4Hz 2Hz 0.125Hz PCLK / 128 0.25s 0.5s 8s 64Hz 32Hz 2Hz PCLK / 8* 15.63ms 31.25ms 0.5s *PCLK/8 mode is default after reset Table 3. Pre-scaled clock frequency and periods when WDT_PRE = 0 and PCLK = 32,768Hz
PCLK / 2048
16Hz 62.5ms 32Hz 31.25ms 128Hz 7.81ms 256Hz 3.906ms 4096Hz 244.14us
16Hz 62.5ms 32Hz 31.25ms 128Hz 7.81ms 256Hz 3.906ms 4096Hz 244.14us
WDT_CS
Frequency/ Period
WDT_PRE = 15 Frequency/ Period
WDT_START (x64) Frequency/ Period
WDT_INT (x128) Frequency/ Period
WDT_RESET (x2048) Frequency/ Period
16Hz 1Hz 0.0156 Hz 0.00781 Hz 0.00048Hz 62.5ms 1s 64s 128s 2048s 32Hz 2Hz 0.03125Hz 0.0156 Hz 0.000976Hz PCLK / 1024 31.25ms 0.5s 32s 64s 1024s 128Hz 8Hz 0.125Hz 0.0625Hz 0.0039Hz PCLK / 256 7.81ms 125ms 8s 16s 256s 256Hz 16Hz 0.25Hz 0.125Hz 0.00781Hz PCLK / 128 3.906ms 62.5ms 45s 8s 128s 4096Hz 256Hz 4Hz 2Hz 0.125Hz PCLK / 8 244.14us 3.906ms 0.25s 0.5ms 8s Table 4. Pre-scaled clock frequency and periods when WDT_PRE = 15 and PCLK = 32,768Hz
PCLK / 2048
Simulation Mode
We add simulation mode for fast and stable simulation and add two signals to wdt module. wdt_fatst, wdt_noreset are these signals. If wdt_fast is set to high, wdt module output signals ( wdt_start, wdt_int, wdt_reset) occurred more frequently than normal. And wdt_noreset is set to high, wdt module don't generation wdt_reset. In simulation mode, these two signals are all high. To go to simulation mode, see chapter of mode control part.
6
Chapter 11. RTC module
The Real Time Clock (RTC) unit can operate by the backup battery although the system power turns off. The RTC transmits data to CPU as BCD (binary coded decimal) values. The data include second, minute, hour, date, day of the week, month, and year. The RTC unit works with an external 32.768kHz crystal and also can perform the alarm function. The block diagram is shown in Figure 1.
Features
2 data transfer modes - transmission, reception Clock and calendar functions (BCD display) : seconds, minutes, hours, date, day of week, month, year Leap year generator Wake-up (PMWKUP) signal generation: support on the power down mode Alarm interrupt (ALMINT) in normal operation mode Cyclic interrupts: the interrupt cycle may be 1/256 second, 1/64 second, 1/16second, 1/4 second, 1/2 second, or 1 second Round reset function: 30-, 40-, 50-second Current Consumption: 3.5 A (typical) Operation Temperature Range: 0 C ~ 70 C
S5L840F
RTC RTCEXTAL1 RTCXTAL1 RTCOSC Oscillator and Clock Divider Reset Register Leap Year Generator
Watchdog Timer
SEC
MIN
HOUR
DATE
DAY
MON
YEAR
PRI
Control Register & Control
Alarm Generator
PWDN PMWKUP ALMINT
RTC Internal Module Bus APB Interface
AMBA APB(Advanced Peripheral Bus)
Figure 1. Top block diagram
Pin Description
The signals of Real Time Clock are divided into three sets. The first set includes the APB signals to configure the control registers. Another is to handshake with the Power Management block while in power down mode and relating to interrupt controller. The final is a related crystal signal that will be applied to offchip crystal.
Table 1-1a. APB Interface Signals Name PCLK PRESETn PENABLE PSELPTC PWRITE PADDR[7:0] Type In In In In In In Source/ Destination AMBA APB AMBA APB AMBA APB AMBA APB AMBA APB AMBA APB APB bus clock. Active low. Global reset signal. APB enable signal. APB selection signal. APB read write signal. APB address bus. Description
Table 1-1b. APB Interface Signals Name PWDATA[15:0] PRDATA[15:0] Type In Out Source/ Destination AMBA APB AMBA APB Description APB write data bus. APB read data bus.
2
S5L840F
Table 1-2. Power Management and Interrupt Controller Interface Signals Name PWDN PMWKUP Type In Out Source/ Destination Power Management Power Management Interrupt Controller Interrupt Controller Description
Watchdog Timer
ALMINT
Out
PRI
Out
When this signal is high, RTC is operated by backup battery. This signal is to wake up the power management. While power down mode, this signal can be used to wake up power management unit. Active high. When not power down mode, alarm enable bit in RTC was set and alarm time is matched by this signal that RTC requests a interrupt to interrupt controller. Active high. This signal is to indicate 1/256 second, 1/64 second, 1/16 second, 1/4 second , 1/2 second, or 1 second. Description Clock from clkgen Unit (i_rclk)
Table 1-3. Crystal Interface Signals Name RTCEXTAL1 Type In Source/ Destination Clkgen Unit
Table 1-4. Scan Test Interface Signals Name TMS SCAN_IN SCAN_EN SCAN_OUT Type In In In Out Source/ Destination Testmode Testmux Testmux Testmux Description RTC scan mode selection signal Scan serial input data Scan serial data enable Scan serial output data
Function Description
System clock frequency control
The leap year generator calculates which the last date of each month is 28,29,30 or 31 that is based on data from BCDDAY, BCDMON, and BCDYEAR. This also considers leap years in deciding the last date. A 16 bit counter can just represent four BCD digits, so it can decide whether any year is a leap year or not.
System Power Operation
It is required to set bit 1 of the RTCCON register for interfacing between CPU and RTC logic. An one second error can occur when the CPU reads or writes data into BCD counters and this can cause the change of the higher time units. When the CPU reads/writes data to/from the BCD counters, another time unit may be changed if BCDSEC register is overflowed. To avoid this problem, the CPU should reset BCDSEC register to 00h. The reading sequence of the BCD counters is BCDYEAR, BCDMON, BCDDATE, BCDDAY, BCDHOUR, BCDMIN, and BCDSEC. It is required to read it again from BCDYEAR to BCDSEC if BCDSEC is zero.
3
S5L840F Alarm Function
Watchdog Timer
The RTC generates alarm signal at specified time in the power down mode or normal operation mode. In normal operation mode, the alarm interrupt (ALMINT) is activated and in the power down mode the power management wake up (PMWKUP) signal is activated. The RTC alarm register, RTCALM, determines the alarm enable and the condition of the alarm time setting. Note that the PWDN signal determines whether the normal operation or power down mode.
Round Reset Function
The round reset function can be performed by the RTC round reset register, RTCRST. You can select the round boundary (30, 40, or 50 sec) of the second carry generation and the second value is rounded to zero value in the round reset operation. For example, when the current time is 23:37:47 and the round boundary is selected as 40 sec, the round reset operation changes the current time with 23:38:00.
RTC Operation
Initial Settings of Registers after Power-on
Almost of all registers (except BCD registers) have initial value after the power is turned on.
Setting the Time
Figure 2. shows how to set the time when clock is stopped. This works when the entire calendar or clock is to be set.
To reset the divider circuit and set the counter
Stop clock, Reset divider circuit
Write "1" to CLKRST and "1" to STARTB in the RTCCON register Order is irrelevant
Set seconds, minutes, hour, date, day of the week, month and year
Start Clock
Write "0" to STARTB in the RTCCON register
Figure 2. Setting the Time
4
S5L840F Alarm Function
Watchdog Timer
Figure 3. shows how to use the alarm function. Alarms can be generated using the seconds, minutes, hours, day of week, date, month, year or any combination of these. Set the ALMEN bit (bit 7) in the register on which the alarm is placed to "1", and then set the alarm time. Clear the ALMEN bit in the register on which the alarm is placed to "0". When the INTMODE bit of RTCIM register is high, and the clock and alarm times match, "1" is set in the PEND bit of RTCPEND register. The detection of alarm can be checked with reading the PEND bit.
Clock running
BCD clock is running
Set whether to use alam interrupts that are level or edge
When using interrupts, the interrupt type bit (INTMODE) is set or not.
Set alarm time
Monitor alarm time (wait for interrupt)
Figure 3. Using the Alarm Function
5
S5L840F
Watchdog Timer
Programmer's Model
Register memory map
RTC_BASE : 0x 3D20_0000 ( Virtual base address : 0x3A 4000) Register RTCCON RTCRST RTCALM ALMSEC ALMMIN ALMHOUR ALMDATE ALMDAY ALMMON ALMYEAR BCDSEC BCDMIN BCDHOUR BCDDATE BCDDAY BCDMON BCDYEAR RTCIM RTCPEND Address Base + 0x00 Base + 0x04 Base + 0x08 Base + 0x0C Base + 0x10 Base + 0x14 Base + 0x18 Base + 0x1C Base + 0x20 Base + 0x24 Base + 0x28 Base + 0x2C Base + 0x30 Base + 0x34 Base + 0x38 Base + 0x3C Base + 0x40 Base + 0x44 Base + 0x48 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description RTC Control Register RTC Round Reset Register RTC Alarm Control Register Alarm Second Data Register Alarm Minute Data Register Alarm Hour Data Register Alarm Date Data Register Alarm Register Alarm Month Data Register Alarm Year Data Register BCD Second Register BCD Minute Register BCD Hour Register BCD Date Register BCD Day of Week Register BCD Month Register BCD Year Register RTC Interrupt Mode Register RTC Interrupt Pending Register 0x00 0x0000 0x00 0x00 Day of Week Data Reset value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
RTC Control Register (RTCCON)
RTCCON register consists of 6-bits such as STARTB that controls to run the normal counters, RTCEN that controls the read/write enable of the BCD registers, CLKSEL, CNTSEL, and CLKRST for BCD counters testing. RTCEN bit controls all interfaces between the CPU and the RTC, so it should be set to '1' in an initialization routine to enable data transfer after a system reset. Instead of working BCD with 1Hz, CLKSEL bit enables the operation of BCD counters with an external clock which is applied through the pin EXTAL1 to the test BCD counters. CNTSEL bit converts the dependent
operation of BCD counters into independent counters for the test. CLKRST resets the frequency divided logic in the RTC. OSCEN bit controls the path from input of Crystal to the output of divider logic. If this bit is high, the output of
6
S5L840F
Watchdog Timer
divider is 1 Hz clock. To purpose of testing that oscillator circuit and divider block, this bit is implemented.
Table 1-6. RTC Control Register (RTCCON) RTCCON STARTB RTCEN CLKSEL CNTSEL CLKRST OSCEN Bit [0] [1] [2] [3] [4] [5] Description RTC start bit 0 : RUN 1: Halt RTC write enable bit 0 : Disable 1: Enable BCD counter test clock set bit 0 : EXTAL1 divided clock (1 Hz) 1 : Reserved (EXTAL1 clock : 32.768 kHz) BCD count test type set bit 0 : Merge BCD counters 1: Reserved (Separate BCD counters) RTC clock count set bit 0 : No reset 1: reset Oscillator and Divider circuit test enable bit 0 : Disable 1 : Enable Initial State 0 0 0 0 0 0
RTC Alarm Control Register (RTCALM) RTCALM register determines the alarm enable and the condition of the alarm time setting. Note that RTCALM register generates the alarm signal through both ALMINT and PMWKUP in power down mode, while only ALMINT in normal operation mode.
Table 1-7a. RTC Alarm Control Register (RTCALM) RTCCON SECEN MINEN HOUREN DATEEN DAYEN Bit [0] [1] [2] [3] [4] Description Second alarm enable bit 0 : Disable 1 : Enable Minute alarm enable bit 0 : Disable 1 : Enable Hour alarm enable bit 0 : Disable 1 : Enable Date alarm enable bit 0 : Disable 1 : Enable Day of week alarm enable bit 0 : Disable 1 : Enable Initial State 0 0 0 0 0
Table 1-7b. RTC Alarm Control Register (RTCALM) RTCCON MONEN YEAREN ALMEN Bit [5] [6] [7] Description Month alarm enable bit (reserved bit) For alarm function, this bit should be set. Year alarm enable bit (reserved bit) For alarm function, this bit should be set. Alarm global enable bit 0 : Disable 1 : Enable Initial State 0 0 0
7
S5L840F
Alarm Second Data Register (ALMSEC) Table 1-8. Alarm Second Data Register (ALMSEC) ALMSEC SECDATA Reserved Bit [6:0] [7] Description BCD value for alarm second bits [3:0] bit is from 0 to 9 [6:4] bit is from 0 to 5
Watchdog Timer
Initial State 0 0
Alarm Minute Data Register (ALMMIN) Table 1-9. Alarm Minute Data Register (ALMMIN) ALMMIN MINDATA Reserved Bit [6:0] [7] Description BCD value for alarm second bits [3:0] bit is from 0 to 9 [6:4] bit is from 0 to 5 Initial State 0 0
Alarm Hour Data Register (ALMHOUR) Table 1-10. Alarm Hour Data Register (ALMHOUR) ALMHOUR HOURDATA Reserved Bit [5:0] [7:6] Description BCD value for alarm hour bits [3:0] bit is from 0 to 9 [5:4] bit is from 0 to 2 Initial State 0 0
Alarm Date Data Register (ALMDATE) Table 1-11. Alarm Date Data Register (ALMDATE) ALMDATE DATEDATA Bit [5:0] Description BCD value for alarm date, from 0 to 28, 29, 30, 31 (decimal : 01 ~ 31) [3:0] bit is from 0 to 9 [5:4] bit is from 0 to 3 Initial State 0
Reserved
[7:6]
0
Alarm Day of Week Data Register (ALMDAY)
8
S5L840F
Table 1-12. Alarm Day of Week Data Register (ALMDAY) ALMDAY DAYDATA Bit [2:0] Description BCD value for alarm day bits [2:0] bit is from 0 to 6 000 : Sunday 001 : Monday 010 : Tuesday 011 : Wednesday 100 : Thursday 101 : Friday 110 : Saturday
Watchdog Timer
Initial State 0
Reserved
[7:3]
0
Alarm Month Data Register (ALMMON) Table 1-13. Alarm Month Data Register (ALMMON) ALMMON MONDATA Reserved Bit [4:0] [7:5] Description BCD value for alarm month bits [3:0] bit is from 0 to 9 [4] bit is from 0 to 1 Initial State 0 0
Alarm Year Data Register (ALMYEAR) Table 1-14. Alarm Year Data Register (ALMYEAR) ALMYEAR YEARDATA Bit [15:0] Description BCD value for alarm year bits [7:0] bit is from 0 to 99 [15:8] bit is from 0 to 99 Initial State 0
RTC Round Reset Register (RTCRST) Table 1-15. RTC Round Reset Register (RTCRST) RTCRST SECCR Bit [2:0] Description Round boundary for second generation bits 011 : over than 30 sec 100 : over than 40 sec 101 : over than 50 sec Round second reset enable bit 0 : Disable 1 : Enable carry Initial State 0
SRSTEN Reserved
[3] [7:5]
0 0
BCD Second Data Register (BCDSEC) Table 1-16. BCD Second Data Register (BCDSEC) BCDSEC SECDATA Bit [6:0] Description BCD value for second bits Initial State Undef.
9
S5L840F
[3:0] bit is from 0 to 9 [6:4] bit is from 0 to 5 Reserved [7]
Watchdog Timer
-
BCD Minute Data Register (BCDMIN) Table 1-17. BCD Minute Data Register (BCDMIN) BCDMIN MINDATA Reserved Bit [6:0] [7] Description BCD value for minute bits [3:0] bit is from 0 to 9 [6:4] bit is from 0 to 5 Initial State Undef. -
BCD Hour Data Register (BCDHOUR) Table 1-18. BCD Hour Data Register (BCDHOUR) BCDHOUR HOURDATA Reserved Bit [5:0] [7:6] Description BCD value for hour bits [3:0] bit is from 0 to 9 [5:4] bit is from 0 to 2 Initial State Undef. -
BCD Date Data Register (BCDDATE) Table 1-19. BCD Date Data Register (BCDDATE) BCDDATE DATEDATA Reserved Bit [5:0] [7:6] Description BCD value for date bits(decimal : 01 ~ 31) [3:0] bit is from 0 to 9 [5:4] bit is from 0 to 3 Initial State Undef. -
BCD Day of Week Data Register (BCDDAY) Table 1-20. BCD Day of Week Data Register (BCDDAY) BCDDAY DATEDAY Bit [2:0] Description BCD value for date bits [2:0] bit is from 0 to 6 000 : Sunday 001 : Monday 010 : Tuesday 011 : Wednesday 100 : Thursday 101 : Friday 110 : Saturday Initial State Undef.
Reserved
[7:3]
-
BCD Month Data Register (BCDMON)
10
S5L840F
Table 1-20. BCD Month Data Register (BCDMON) BCDMON MONDATA Reserved Bit [4:0] [7:5] Description BCD value for month bits [3:0] bit is from 0 to 9 [4] bit is from 0 to 1
Watchdog Timer
Initial State Undef. -
BCD Year Data Register (BCDYEAR) Table 1-21. BCD Year Data Register (BCDYEAR) BCDYEAR YEARDATA Bit [15:0] Description BCD value for year bits [7:0] bit is from 0 to 99 [15:8] bit is from 0 to 99 Initial State Undef.
RTC Interrupt Mode Register (RTCIM) Periodic Interrupt Mode (PEIMODE): Indicates generation of interrupt with the period designated by the PES bits. When set to "1" PEIMODE generates periodic interrupts.
Table 1-22. RTC Interrupt Mode Register (RTCIM) RTCIM INTMODE Bit [1:0] Description Interrupt mode selection bit x0 : Disable alarm interrupt mode. x1 : Enable alarm interrupt mode. 01 : Supports on the edge alarm interrupt. 11 : Supports on the level alarm interrupt. Periodic interrupt mode bit 0 : Interrupts not generated with the period designated by the PES bits. 1 : Interrupts generated with the period designated by the PES bits. These bits specify the periodic interrupt. 000 : No periodic interrupt generated 001 : Periodic interrupt generated every 1/256 second 010 : Periodic interrupt generated every 1/64 second 011 : Periodic interrupt generated every 1/16 second 100 : Periodic interrupt generated every 1/4 second 101 : Periodic interrupt generated every 1/2 second 110 : Periodic interrupt generated every 1 second 111 : reserved Initial State 0
PEIMODE
[2]
0
PES
[5:3]
0
Reserved
[7:6]
0
11
S5L840F
RTC Interrupt Pending Register (RTCPEND) Table 1-23. RTC Interrupt Pending Register (RTCPEND) RTCPEND PEND Reserved Bit [0] [7:1] Description Interrupt pending enable bit 0 : PEND bit is cleared. 1 : PEND bit is pending.
Watchdog Timer
Initial State 0 0
Timing Diagram
Interfacing RTC to APB
Interfacing the RTC to the APB is described in: Read transfer Write transfer
Figure 5. illustrates a read transfer.
T1 PCLK PADDR[7:0] PWRITE PSELRTC PENABLE PRDATA
T2
T3
T4
T5
Address 1
Data 1 data sampled by APB bridge
Figure 5. A Read Transfer
12
S5L840F
Figure 6. illustrates a write transfer.
Watchdog Timer
T1 PCLK PADDR[7:0] PWRITE PSELRTC PENABLE PWDATA RTC Registers
T2
T3
T4
T5
Address 1
Data 1 Data 1
Figure 6. A Write Transfer
13
Chapter 12. Timer module
S5L840F has internally two timers. They are named as timer A, timer C. Timer A has the full function. However, timer C has a limited function that is derived from the full function of timer A. The supported modes of the full functional timer are interval mode, PWM (Pulse Width Modulation) mode, one-shot PWM mode, and capture mode. The full functional timer has internally one counter register (TM_CNT), one pre-scale register (TM_PRE), and two data registers (TM_DATA0, TM_DATA1). The TM_CNT is incremented by a pre-scaled clock that is pre-scaled by TM_PRE value from an external clock or internally selected clock. The role of TM_DATA0 and TM_DATA1 is different for each mode. The timer with paritial funcion (Timer C) does not have the TM_DATA1 register because of its functional limit.
FEATURES
Four 16-bits timer: Timer A, Timer C Timer A support interval mode, PWM mode, one-shot mode, and capture mode Timer C support interval mode Pre-scaling the counting clock with the 10-bits pre-scale register (TM_PRE) 0 ~ 100 % duty ratio PWM signal generation
S5L840F
16 BITS TIMER
BLOCK DIAGRAM
PCLK / 64 PCLK Clock Division PCLK / 16 PCLK / 4 PCLK / 2 ExtCLK1 M U X count clock overflow TM_OVF_INT 16-bit Counter (TM_CNT) clear 10-bit TM_PRE
ExtCLK0 TM_CS
capture interrupt
MUX
TM_MAT_INT0 TM_MAT_INT1
Buffer
Comparator
Comparator
TMCAP
Edge Detector
TM_OUT
Capture Buffer register Buffer register
Data register 1 (TM_DATA1)
Data register 0 (TM_DATA0)
Figure 1. Block diagram for timer A
Timer A Prescaler
Timer A Compare
Timer C Prescaler
Timer C Compare
Timer A Control Register
Timer A Capture
Timer C Control Register
Figure 2. Timer Block Diagram
PIN DESCRIPTION
Pin Name reset_n Clk Clk_ext0 Width 1 1 4 I/O I I I Description Global reset Global clock External clock 0 for internal counting 0 External clock 0 for Timer A 1 External clock 0 for Timer B 2 External clock 0 for Timer C 3 External clock 0 for Timer D External clock 1 for internal counting 0 External clock 1 for Timer A 1 External clock 1 for Timer B
Clk_ext1
4
I
2
S5L840F
2 External clock 1 for Timer C 3 External clock 1 for Timer D Interrupt APB selection signal APB enable signal APB write/read signal APB address APB data input APB data output External signal to be captured PWM signal output pwm_out[0] Timer A PWM output pwm_out[1] Timer B PWM output
16 BITS TIMER
intr APB Interface psel penable pwrite paddr pwdata prdata External Interface cap_port pwm_out
4 1 1 1 7 32 32 2 2
O I I I I I O I O
reset_n Global reset to reset the internal register clk APB clock (main clock) clk_ext0/1 Clk_ext0 and clk_ext1 are the external clock ports to count the internal counter. As the divided clock from the main clock mainly counts the internal counter, the counter value may not be accurate for some application. In that case, external accurate clock is used for more accurate counting operation. The positive edge of external clocks is internally detected by the main clock. So the external clock frequency should be lower than the main clock. intr When an interrupt condition occurs, an interrupt request is generated to the CPU core. APB interface signals (psel, penable, pwrite, paddr, pwdata, prdata) AMBA APB interface signals cap_port Positive edge or negative edge of external signals is detected and the time of these events are captured to the internal data registers. As these cap ports get external signals, they are digitally filtered in the internal capture block with 5 tabs. So glitches within 5 main clock periods in the cap port are digitally filtered out. pwm_out In interval mode and PWM mode, when the value of counter equals to that of data register, a match interrupt occurs and the pwm_out signal is toggled. This port is used to generate the toggling signal in interval mode or PWM signal in PWM mode.
3
S5L840F
16 BITS TIMER
REGISTER MAP
Name Width Timer A Registers 32 TACON 32 TACMD TADATA0 32 TADATA1 32 32 TAPRE 32 TACNT Timer C Registers 32 TCCON 32 TCCMD TCDATA0 32 32 TCRE 32 TCCNT Address(Virtual) 0x3c70 0000(0x38 e000) 0x3c70 0004(0x38 e004) 0x3c70 0008(0x38 e008) 0x3c70 000c(0x38 e00c) 0x3c70 0010(0x38 e010) 0x3c70 0014(0x38 e014) 0x3c70 0040(0x38 e040) 0x3c70 0044(0x38 e044) 0x3c70 0048(0x38 e048) 0x3c70 0050(0x38 e050) 0x3c70 0054(0x38 e054) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Control Register Command Register Data0 Register Data1 Register Prescale Register Counter Register Control Register Command Register Data0 Register Prescale Register Counter Register Reset 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000
4
S5L840F
16 BITS TIMER
TIMER A REGISTERS
TACON Name TACON 31 15 30 14 29 13 Width 32 28 12 27 11 Address 0x3c70 0000 26 25 R/W R/W 24 8 23 7 Description Control Register for timer A 22 6 21 5 20 4 19 3 18 2 Reset 0x0000 0000 17 1 16 0
10 9 TA_CS Type R R/W
Bits 20 18
Name TA_OUT TA_OVF
17
TA_INT1
R/W
16
TA_INT0
R/W
14
TA_OVF_EN
R/W
13
TA_INT1_EN
R/W
12
TA_INT0_EN
R/W
11
TA_START
R/W
Description The PWM output in interval/PWM/one-shot modes Overflow interrupt status. Although the interrupt is disabled, this field is updated when an overflow interrupt occurs. - Writing one clears this flag - Writing zero has no effect Match interrupt 1 status. Although the interrupt is disabled, this field is updated when a match interrupt 1 occurs. - Writing one clears this flag - Writing zero has no effect Match interrupt 0 status. Although the interrupt is disabled, this field is updated when a match interrupt 0 occurs. - Writing one clears this flag - Writing zero has no effect Enable the overflow interrupt. When disabled, overflow interrupt sets the TA_OVF but it does not generate an interrupt request signal to external interrupt control unit. 0 Disable the overflow interrupt 1 Enable the overflow interrupt Enable the match interrupt 1. When disabled, match interrupt 1 sets the TA_INT1 but it does not generate an interrupt request signal to external interrupt control unit. 0 Disable the overflow interrupt 1 Enable the overflow interrupt Enable the match interrupt 0. When disabled, match interrupt 0 sets the TA_INT0 but it does not generate an interrupt request signal to external interrupt control unit. 0 Disable the overflow interrupt 1 Enable the overflow interrupt In interval/PWM/one-shot modes, this field is set to the TA_OUT by clear operation (writing one to TA_CLR). In PWM and one-shot mode, whenever an MAT_INT1 occurs, this value is also updated to the TA_OUT. In interval mode, if MAT_INT0 occurs, this value is updated to the TA_OUT.
Rising clear Clear the cou
Rising clear Clear the cou
5
S5L840F
16 BITS TIMER
Timer clock source selection 3'b000 PCLK / 2 3'b001 PCLK / 4 3'b010 PCLK / 16 3'b011 PCLK / 64 3'b10x External clock 0 3'b11x External clock 1 In capture mode, 0 Rising clear mode. Clear the counter when a rising edge is detected. 1 Falling clear mode. Clear the counter when falling edge is detected Operation mode selection 2'b00 Interval mode 2'b01 PWM mode 2'b10 One-shot mode 2'b11 Capture mode
10:8
TA_CS
R/W
7
TA_CAP_MODE
R/W
5:4
TA_MODE_SEL
R/W
TACMD Name TACMD 31 15 30 14 29 13 Width 32 28 12 27 11 Address 0x3c70 0004 26 10 25 9 R/W R/W 24 8 23 7 Description Command Register for timer A 22 6 21 5 20 4 19 3 18 2 Reset 0x0000 0000 17 1 16 0
Bits
Name
Type
1
TA_CLR
W
0
TA_EN
R/W
Description Clear operation. This field is always zero when read. 0 Nothing occurs 1 Initialize the timer. - Clear the counter register. - The value of TA_START is set to TA_OUT. - TA_DATA0 and TA_DATA1 are updated to the internal buffers - Initialize the state of the previously captured signal. Timer enable command 0 Disable the timer 1 Enable the timer
TADATA0 Name TADATA0
6
Width 32
Address 0x3c70 0008
R/W R/W
Description Data register
Reset 0x0000 0000
S5L840F
16 BITS TIMER
31 15
30 14
29 13
28 12
27 11
26 10
25 9
24
23
22 6
21 5
20 4
19 3
18 2
17 1
16 0
8 7 TA_DATA0
Bits
Name
Type
15:0
TA_DATA0
R/W
Description This field is used differently by the operation mode. Interval mode The target counting value is stored in this field. When the counter value equals to this register, a MAT_INT0 interrupt is generated. Whenever an MAT_INT0 occurs or clear operation is executed, this value is updated to the internal data buffer 0. PWM mode/ The target counting value is stored in this One-shot field. When the counter value equals to mode this register, a MAT_INT0 interrupt is generated. This field is updated to the internal data buffer 0 when MAT_INT1 occurs or when clear operation is executed. Capture mode In rising-edge clear mode, the captured data at the falling edge is stored to this register. In falling-edge clear mode, the captured data at the rising edge is stored to this register.
TADATA1 Name TADATA1 31 15 30 14 29 13 Width 32 28 12 27 11 Address 0x3c70 000c 26 10 25 9 R/W R/W 24 23 Description Data register 22 6 21 5 20 4 19 3 18 2 Reset 0x0000 0000 17 1 16 0
8 7 TA_DATA1
Bits 15:0
Name TA_DATA1
Type R/W
Description This field is used differently by the operation mode. Interval mode Not used PWM mode/ The target counting value is stored in this One-shot field. When the counter value equals to mode this register, a MAT_INT1 interrupt is
7
S5L840F
16 BITS TIMER
generated. This field is updated to the internal data buffer 1 when MAT_INT1 occurs or when clear operation is executed. In rising-edge clear mode, the captured data at the rising edge is stored to this register. In falling-edge clear mode, the captured data at the falling edge is stored to this register.
Capture mode
TAPRE Name TAPRE 31 15 30 14 29 13 Width 32 28 12 27 11 Address 0x3c70 0010 26 10 25 9 R/W R/W 24 8 23 7 Description Pre-scale register 22 6 21 20 19 3 18 2 Reset 0x0000 0000 17 1 16 0
5 4 TA_PRE Description
Bits 9:0 TACNT
Name TA_PRE
Type R/W
Pre-scale value
Name TACNT 31 15 30 14 29 13
Width 32 28 12 27 11
Address 0x3c70 0014 26 10 25 9
R/W R 24 23
Description Counter register 22 6 21 5 20 4 19 3 18 2
Reset 0x0000 0000 17 1 16 0
8 7 TA_CNT
Bits 15:0
Name TA_CNT
Type R
Description Counter register
8
S5L840F
16 BITS TIMER
TIMER C REGISTERS
TCCON Name TCCON 31 15 30 14 29 13 Width 32 28 12 27 11 Address 0x3c70 0040 26 25 R/W R/W 24 8 23 7 Description Control Register for timer C 22 6 21 5 20 4 19 3 18 2 Reset 0x0000 0000 17 1 16 0
10 9 TC_CS Type R/W R/W
Bits 18 16 14 12
Name Reserved TC_INT0 Reserved TC_INT0_EN
10:8
TC_CS
R/W
Description This flag should be set to 0. Match interrupt 0 status - Writing one clears this flag - Writing zero has no effect This flag should be set to 0 Enable the match interrupt 0. When disabled, match interrupt 0 sets the TC_INT0 but it does not generate an interrupt request signal to external interrupt control unit. 0 Disable the overflow interrupt Rising clear 1 Enable the overflow interrupt Clear the cou Timer clock source selection 3'b000 PCLK / 2 3'b001 PCLK / 4 3'b010 PCLK / 16 3'b011 PCLK / 64 3'b10x External clock 0 3'b11x External clock 1
TCCMD Name TCCMD 31 15 30 14 29 13 Width 32 28 12 27 11 Address 0x3c70 0044 26 10 25 9 R/W R/W 24 8 23 7 Description Command Register for timer C 22 6 21 5 20 4 19 3 18 2 Reset 0x0000 0000 17 1 16 0
Bits
Name
Type
Description
9
S5L840F
16 BITS TIMER
Initialize the timer 0 Nothing occurs 1 Initialize the timer. - Clear the counter register. - TC_DATA0 is updated to the internal buffers - Initialize the state of the previously captured signal. Timer enable command 0 Disable the timer 1 Enable the timer
1
TC_CLR
W
0
TC_EN
R/W
TCDATA0 Name TCDATA0 31 15 30 14 29 13 Width 32 28 12 27 11 Address 0x3c70 0048 26 10 25 9 R/W R/W 24 23 Description Data register 22 6 21 5 20 4 19 3 18 2 Reset 0x0000 0000 17 1 16 0
8 7 TC_DATA0
Bits
Name
Type
15:0
TC_DATA0
R/W
Description This field is used differently by the operation mode. Interval mode The target counting value is stored in this field. When the counter value equals to this register, a MAT_INT0 interrupt is generated. Whenever an MAT_INT0 occurs or clear operation is executed, this value is updated to the internal data buffer 0 for next comparison.
TCPRE Name TCPRE 31 15 30 14 29 13 Width 32 28 12 27 11 Address 0x3c70 0050 26 10 25 9 R/W R/W 24 8 23 7 Description Pre-scale register 22 6 21 20 19 3 18 2 Reset 0x0000 0000 17 1 16 0
5 4 TC_PRE Description
Bits 9:0
10
Name TC_PRE
Type R/W
Pre-scale value
S5L840F
16 BITS TIMER
TCCNT Name TCCNT 31 15 30 14 29 13 Width 32 28 12 27 11 Address 0x3c70 0054 26 10 25 9 R/W R 24 23 Description Counter register 22 6 21 5 20 4 19 3 18 2 Reset 0x0000 0000 17 1 16 0
8 7 TC_CNT
Bits 15:0
Name TC_CNT
Type R
Description Counter register
11
S5L840F
16 BITS TIMER
INTERVAL MODE
This mode is selected by setting TM_MODE_SEL to 0b00x. When the (TM_CNT + 1) value equals to the buffer corresponding to TM_DATA0 in the operation, an interrupt (TM_MAT_INT0) occurs, the value of the TM_CNT is cleared to zero and TM_CNT counts up again. In this mode, TM_DATA1 is not used. The TM_OUT pin of a timer is used to generate a signal that is toggled by TM_MAT_INT0. The waveform of the signal generated in this mode is in Figure 2. As you can see, changing the value of TM_DATA0 varies the width of the pulse. TM_DATA0 can be updated during the operation but the effect of that value occurs at the next phase.
200 150 TM_CNT value 0 Start TM_DATA0=150 Write Write TM_DATA0=100 TM_DATA0=200 100 200
Interrupt (TM_MAT_INT0)
Fig 2. Interval mode operation The detailed waveform is shown in Figure 3.
PCLK COUNTING ENABLE TM_CNT INTR (mat_int0) TM_OUT TM_EN TM_CLR DATA0_BUF 0003 0000 0001 0002 0000
Interval mode, TM_DATA0 = 3, TM_START = 1
Figure 3. Waveform in interval mode
PWM (Pulse Width Modulation) MODE
Like the interval mode, the TM_CNT value is compared to the two buffers that are updated with the values of TM_DATA0 and TM_DATA1 register. When (TM_CNT + 1) is equal to the buffer of TM_DATA0, TM_MAT_INT0 interrupt occurs and the timer continues the counting operation
12
S5L840F
16 BITS TIMER
without clearing the counter. When (TM_CNT + 1) is equal to the buffer of TM_DATA1, the timer generates TM_MAT_INT1 interrupt, clears theTM_CNT register, and updates the internal buffers with the values of TM_DATA0 register and TM_DATA1 register. For each interrupt, the TM_OUT is toggled. As the values of TM_DATA0 and TM_DATA1 register are updated after the TM_MAT_INT1 interrupt, the new values in TM_DATA0 and TM_DATA1 registers have an effect after TM_MAT_INT1 occurs. This mode is used to generate a configurable PWM signal. The clock period of PWM signal can be set in TM_DATA1 register and the duty ratio can be set in TM_DATA0 register. The operation of this mode is described in the Figure 4.
200 150 TM_CNT value 100 0 TM_DATA1 =200 TM_OUT Start TM_DATA0=150 TM_DATA1=200 (period=200) TM_DATA1 =200 TM_DATA1 =200 TM_DATA1 =100 75 100 50 200 200
Write TM_DATA0 = 100
Write TM_DATA0 = 75
Write TM_DATA0 = 50 TM_DATA1= 100 (period change)
Figure 4. PWM mode operation Depending on the values of the TM_DATA0 and TM_DATA1, the shapes of the PWM signals are different. The detailed waveforms in PWM mode are shown in Figure 6, Figure 7, Figure 8, and Figure 9.
13
S5L840F
PCLK COUNTING ENABLE TM_CNT INTR (mat_int1) INTR (mat_int0) TM_OUT TM_EN TM_CLR DATA0_BUF DATA1_BUF 0001 0002 Initially TM_DATA0 = 1 and TM_DATA1 = 2 PWM mode, TM_DATA0 = 1, TM_DATA1 = 2, TM_START = 1 0000 0001 0000 0001
16 BITS TIMER
Figure 6. PWM signal when TM_DATA0 = 1 and TM_DATA1 = 2
PCLK COUNTING ENABLE TM_CNT INTR (mat_int1) INTR (mat_int0) TM_OUT TM_EN TM_CLR DATA0_BUF DATA1_BUF 0000 0000 Initially TM_DATA0 = 0 and TM_DATA1 = 0 PWM mode, TM_DATA0 = 0, TM_DATA1 = 0, TM_START = 1 0000 0000 0000 0000
Figure 7. PWM signal when TM_DATA0 = 0 and TM_DATA1 = 0
14
S5L840F
PCLK COUNTING ENABLE TM_CNT INTR (mat_int1) INTR (mat_int0) TM_OUT TM_EN TM_CLR DATA0_BUF DATA1_BUF 0000 0002 Initially TM_DATA0 = 0 and TM_DATA1 = 2 PWM mode, TM_DATA0 = 0, TM_DATA1 = 2, TM_START = 1 0000 0001 0000 0001
16 BITS TIMER
Figure 8. PWM signal when TM_DATA0 = 0 and TM_DATA1 = 2 (Duty Ratio = 0 %)
PCLK COUNTING ENABLE TM_CNT INTR (mat_int1) INTR (mat_int0) TM_OUT TM_EN TM_CLR DATA0_BUF DATA1_BUF 0002 0002 Initially TM_DATA0 = 2 and TM_DATA1 = 2 PWM mode, TM_DATA0 = 2, TM_DATA1 = 2, TM_START = 1 0000 0001 0000 0001
Figure 9. PWM signal when TM_DATA0 = 2 and TM_DATA1 = 2 (Duty Ratio = 100 %)
ONE-SHOT MODE
15
S5L840F
16 BITS TIMER
One-shot mode is same as the PWM mode except that only one PWM signal pulse is generated. After generating one PWM signal, the flag, TM_EN, in TM_COM register is cleared to disable the timer. The operation of the one-shot mode is described in Figure 10.
TMCNT value 0 TMDATA1 value TMDATA0 value Clear One-shot pulse width = TMDATA1-TMDATA0
Start
TMDATA0 match
TMDATA1 match
Figure 10. One-shot mode operation
CAPTURE MODE
Capture mode is used to capture the external signal from the TM_CAP. When a timer is enabled in this mode, the internal counter continues the counting and the timer waits an event on the TM_CAP port. When a falling or rising transition occurs on the TM_CAP port, the value of the counter register is captured to the data registers (TM_DATA0 or TM_DATA1) and an interrupt is generated (TM_MAT_INT0 or TM_MAT_INT1). Capture mode has two distinct modes: rising edge clear mode and falling edge clear mode. The TM_CAP_MODE flag in the TMCON register sets these modes. In rising edge clear mode by setting TM_CAP_MODE to 0, when a falling edge is detected, the count value is captured to the TM_DATA0 and an interrupt TM_MAT_INT0 is generated. On the other hand, when a rising edge on the TM_CAP port is detected, the count value is also captured to the TM_DATA1, an interrupt TM_MAT_INT1 is generated and the count register is cleared to zero. In this mode, the internal counter is cleared when an rising event is detected on the TM_CAP port. The detailed description is shown in Fig 8.
16
S5L840F
TMCAP falling edge rising edge
16 BITS TIMER
400 150 TMCNT 0 Clear
450
200
50
Interrupt
TMMAT_INT0 TMDATA0 TMDATA1 xxx xxx
TMMAT_INT1 TMMAT_INT0 150 400
TMMAT_INT1 200 450 50
Fig 8. Capture mode in rising edge clear mode The falling edge clear mode is reverse to the rising edge clear mode. When a rising edge is detected on the TM_CAP port, the count value is captured to TM_DATA0 and an interrupt, TM_MAT_INT0, is generated. When a falling edge occurs, the count value is stored to TM_DATA1, TM_MAT_INT1 occurs and the count register is cleared. By using the capture mode, you can get all the needed information of a PWM signal: duty ratio and the period.
COUNTING CLOCK DIVISION
The internal clock is counted by a clock which is prescaled by TM_PRE register and clock selection. The clock selected by TM_CS is predefined clocks or external clocks. The predefined clocks are derived from the main clock. There are two external clocks. They can be used for accurate sync with an external logic that is not synchronous with the main clock. The internal counter counts up with the rising edge of the external clock. The clock selected by the TM_CS is scaled by the TM_PRE register. The frequency of the scaled clock is as follows: Scaled clock [Hz] = Source clock [Hz] / (TM_PRE + 1) The source clock is the selected clock by the TM_CS. Table 1 and Table 2 shows the frequency and the period for each clock selection. It assumes that the main clock is 121.5 MHz.
17
S5L840F
16 BITS TIMER
TM_CS
Frequency/
Period
1.90 MHz 526.75 ns 7.59 MHz 131.69 ns 30.38 MHz 32.92 ns 60.75 MHz 16.46 ns
TM_PRE = 0 Overflow Count Clock (x65536)
TM_PRE = 1024 Overflow Count Clock (x65536)
Frequency/ Period
1.90 MHz 526.75 ns 7.59 MHz 131.69 ns 30.38 MHz 32.92 ns 60.75 MHz 16.46 ns
Frequency/ Period
28.97 Hz 34.52 ms 115.87 Hz 8.63 ms 463.49 Hz 2.16 ms 926.97 Hz 1.08 ms
Frequency/ Period
1.85 KHz 539.39 ms 7.42 KHz 134.85 ms 29.66 KHz 33.71 ms 59.33 KHz 16.86 ms
Frequency/ Period
0.03 Hz 35.35 s 0.11 Hz 8.84 s 0.45 Hz 2.21 s 0.91 Hz 1.10 s
Main Clock / 64 Main Clock / 16 Main Clock / 4 Main Clock / 2
Table 1. Pre-scaled clock frequency and period when main clock = 121.5 MHz
18
S5L840F
16 BITS TIMER
19
S3C49F8X MultiMediaCard CONTROLLER
NAND Flash Memory Controller
OVERVIEW
This module can control the interface of the external NAND Flash memory.
Features
Flash Memory Controller(FMC) supports the following function. supports 64/128/256/512Mbit,1G, 2G,4Gbit NAND flash memory made by Samsung. can be connected up to 3 flash memory. supports only one flash memory at a time. ECC supported For ECC, the parity bit encoding and decoding
1/13
S3C49F8X MultiMediaCard CONTROLLER
Block Diagram
d nack d nreq readybusy fmc_rbb_insample fmc_dma fmc_out
fmio input fmio enb fmio output
ceb0 PCLK PRESETn PENABLE PSELFMC PADDR PWRITE PWDATA fmc_reg_n_dbuf fmc_rs_dec fmc_rs_dec_16 fmc_ecc_misc fmc_rs_enc fmc_fsm fmc_rs_enc_16 ceb1 ceb2 web reb wpb cle ale
PRDATA
fmc_synd_outbuf_ctrl
2/13
S3C49F8X MultiMediaCard CONTROLLER
Pin description for flash memory Diagram
part
port name
PCLK PRESETn PSELFMC
Description
APB
PADDR[5:0] PWRITE PWDATA[15:0] PRDATA[15:0] fmio_enb fmio_input[15:0] fmio_output[15:0] ceb0 ceb1 ceb2
AMBA APB protocol
Flash IO output enable, low active. Flash IO input Flash IO output Chip0 select Chip1 select Chip2 select Write enable Read enable Spare area enable Wrote protect Command latch enable Address latch enable DMA acknowledge DMA request (deleted)
Flash web reb seb wpb cle ale D_nack DMA D_nreq
3/13
S3C49F8X MultiMediaCard CONTROLLER
Function description
OVERVIEW This FMC support 64Mb, 128Mb, 256Mb, 512Mb, 1Gb, 2Gb and 4Gb NAND flash memory which are made by SAMSUNG. User can do that FMC is enabled or disabled using control register in FMC. The ECC scheme used in this FMC is RS-CODE. The main features are : - NAND Flash Controller - Support 64Mb/128Mb/256Mb/512Mb/1Gb/2Gb/4Gb NAND Flash components - Support 8bit or 16bit interface. - Embedded 1-symbol ECC (RS-CODE) Encoder/Decoder - There are two ways for data transfer, by CPU or DMA. .
Flash Memory Controller Operation description After reset is active, FMC will be disabled. All of registers are cleared in this state. FMC is enabled or disabled by control register. The operation sequence is the following : 1) Read the ID register for getting the information of the connected external Flash memory. From the content of ID register, User can also get the version of FM. 2) Set the density register and control register. The signal named by fmc_en in control register is the signal for FMC to be enabled or disabled. After this signal is toggled from low to high, the density register has to be set again. In case of ECC mode, after write operation, the syndrome data generated has to be saved for read operation. In case that read operation is executed in ECC mode, User has to write the syndrome data in syndrome register prior to reading. 3) User can get the status of the current operation by reading the status register.
4/13
S3C49F8X MultiMediaCard CONTROLLER
Flash Memory Controller register
ADDRESS
Base address + 0x00 Base address + 0x04 Base address + 0x08 Base address + 0x0C Base address + 0x10 Base address + 0x14 Base address + 0x18 Base address + 0x1C Base address + 0x20 Base address + 0x24 Base address + 0x28 Base address + 0x2C Base address + 0x30 Base address + 0x34 Base address + 0x38 Base address + 0x3C Base address + 0x40 Base address + 0x60 Base address + 0x64 Base address + 0x68 Base address + 0x6C Base address + 0x80 Base address + 0x84 Base address + 0x88 Base address + 0x8C Base address + 0x90 Base address + 0x94 Base address + 0x98 Base address + 0x9C Base address + 0xA0 Base address + 0xA4
R/W
R/W R/W R/W R/W R/W R/W R R R R R R R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
REGISTER NAME
Command Register Column Address Register1 Column Address Register2 Row Address Register1 Row Address Register2 Row Address Register3 Flash Memory Status Register (CMD = 70h) Flash Memory ID Register0 (CMD = 90h) Flash Memory ID Register1 (CMD = 90h) Flash Memory ID Register2 (CMD = 90h) Flash Memory ID Register3 (CMD = 90h) Flash Memory ID Register4 (CMD = 90h) Control Register ECC Decoder Control Register Controller Status Register ECC Decoder Status Register Data Register0 ~ 7 Syndrome data0 generated at write operation Syndrome data1 generated at write operation Syndrome data2 generated at write operation Syndrome data3 generated at write operation Syndrome data0 used for read operation Syndrome data1 used for read operation Syndrome data2 used for read operation Syndrome data3 used for read operation Syndrome data0 used for read operation Syndrome data1 used for read operation Syndrome data2 used for read operation Syndrome data3 used for read operation Density of Flash that will be used FSM of Controller FMCMD FMCADDR1 FMCADDR2 FMRADDR1 FMRADDR2 FMRADDR3 FMRSTATUS FMRID0 FMRID1 FMRID2 FMRID3 FMRID4 FMCTRL FMCDECTRL FMCSTATUS FMCDECSTATUS FMDATARDWR0 ~ 7 FMSYNDOUTRW0 FMSYNDOUTRW1 FMSYNDOUTRW2 FMSYNDOUTRW3 FMSYNDINRW0 FMSYNDINRW1 FMSYNDINRW2 FMSYNDINRW3 FMDEC_RESULT0 FMDEC_RESULT1 FMDEC_RESULT2 FMDEC_RESULT3 FMDENSITY FMTEST
5/13
S3C49F8X MultiMediaCard CONTROLLER
Flash Memory Controller Register Descriptions FMCMD Initial value is 0x00. The command will be sent to FM is written in this register. Bit[15:8] Not used Bit[7:0] Command
Address_n Register (FMCADDRn/FMRADDRn)
Initial valures are 0x00. There are 5 address registers. The column address is written in FMCADDRn and the row address is written in FMRADDRn as to the density type of external Flash Memory. (Ex : 512Mb Read : FMCADDR1 512Mb Erase : FMRADDR1 Bit[15:8] Not used FMRADDR1 FMRADDR2 Bit[7:0] Address FMRADDR2 FMRADDR3 ) FMRADDR3
External Flash Memory Status Register (FMRSTATUS) Initial value is 0x00. After writing 0x70 command(READ STATUS) to FM, FM outputs the contents of FM status. Those content are written in FMRSTATUS register. User can find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully.
Bit[15:8] Not used Bit[7:0] Status of Flash
6/13
S3C49F8X MultiMediaCard CONTROLLER
External Flash Memory IDn Register (FMRIDn) Initial value is 0x00. After writing 0x90 command (READ ID) and an address input, FM(flash memory) send the product identification. Those information is written in FMRIDn register.
Bit[15:8] Not used Bit[7:0] Flash ID
Control Register (FMCTRL)
BIT 0 (ceb1 enable)
OPERATION 0 = disable 1 = enable
FUNCTION The ceb1 is enabled when need to Flash1. The inverse value of this bit outputs to external Flash Memoy/ User can initiate all of registers in FMC. reserved
1 (fmc_en) 2 3 (random_cben) 4.(copybacken) 5 (ecc_en) 6 7 (nWP) 8 (ceb2 enable)
0 = disable 1 = enable 0 = disable 1 = enable 0 = disable 1 = enable 0 = disable 1 = enable
Select whether to use the Copy-back with random data input function Select whether to use the Copy-back function Select whether to use the ECC function reserved
0 = enable 1 = disable 0 = disable 1 = enable
nWP must be high in write mode and don't care in read mode The ceb2 is enabled when need to Flash2. The inverse value of this bit outputs to external Flash Memoy/ The ceb0 is enabled when need to Flash0. The inverse value of this bit outputs to external Flash Memoy/ Select whether the data transfer type is little endian or big endian. Select whether the memoy type is single die or double die. Flash control signal hold the current level for (sig_wait +1) PCLK
9(ceb0 enable)
0 = disable 1 = enable
10 (little endian) 11(version _inf) 14:12 (sig_wait)
0 = little endian 1 = big endian 0 = single die Flash 1 = Double die Flash Ex) PCLK 100MHz = 4 (sig_wait) 50MHz = 2 (sig_wait) 30MHz = 0 (sig_wait)
15 (data_width)
0 : flash IO = x8 1: Flash IO = x16
Select whether the data bit width transferred is 8bit or 16bit.
7/13
S3C49F8X MultiMediaCard CONTROLLER
ECC Control Register (FMCDECTRL) The initial value is 0x0000. After ECC function is enabled, the 4bit named dec_synd_flagN have to be enabled to do read operation with ECC before the contents of syndrome input buffer is changed. The description of each bit is as following:
BIT 0 (dec_synd_flag0) 1 (dec_synd_flag0) 2 (dec_synd_flag0) 3 (dec_synd_flag0) OPERATION 0 = Disable ECC decoder when read operation 1 = Enable ECC decoder when read operation FUNCTION Select whether to use the ECC decoder. Each bit is used for being enable the syndrome data , bit0 is used for 1st 128byte data, bit1 is used for 2nd 128byte data, bit3 is used for 3rd 128 byte data bit4 is used for 4th 128byte data 4 rd_end Read stop While the read operation is executed with ECC, if this bit is high, read operation will be stopped after decode is finished. 5 (clr_inbuf_wr_ptr) 6 dmaen 7 8 15:8 0 = don't care 1 = clear the pointer to 3'b000 0 = disable 1 = enable Reserved Reserved Not used When user don't read data by 512byte, this bit must be used before read operation
8/13
S3C49F8X MultiMediaCard CONTROLLER
FMC Status Register (FMCSTATUS) The initial value is 0x00. User has to check this register while the flow of each program.
BIT 0 (readybusyb) 1 2 (rdid_end_flag) 3 4 5 (status_data_set)
OPERATION 0 = Busy 1 = Ready 1 = Flash ID read end ready. reserved
FUNCTION The status of current operation in FM is busy or
After Flash ID command, all Flash ID bytes are read from Flash Reserved Reserved
0 = not ready 1= ready
When the status data transfers to FMRSTATUS by 70h command, this bit is set. After cpu read FMRSTATUS, this bit will be cleared When `1' is setting, it indicates the last column at that page. Indicate that all address bytes are send to Flash as to command. Indicates Data Buffer(FIFO) are empty during write operation, CPU should write 8 data(width 16) if this bit is high
6 (last_column) 7 (add_send_end) 8(outbuf_rdend)
0 = not last column 1 = last column 1 = address-send-end 1=output buffer empty
9(inbuf0_ready) 10(inbuf1_ready) 11 12 15:13(column_cnt)
1=input buffer full 1=input buffer full
Indicates the first FIFO are full when read operation. CPU can read 8 data Indicates the second FIFO are full when read operation. CPU can read 8 data Reserved Reserved Column_cnt[2:0] While read or write operation is doing, This counter indicate the data number transferred.
9/13
S3C49F8X MultiMediaCard CONTROLLER
ECC Status Register (FMCDECSTATUS) The initial value is 0x0000..
BIT 0 (dec_no_error0) 1 (dec_no_error0) 2 (dec_no_error0) 3 (dec_no_error0) 0 = error 1 = no error
FUNCTION Each bit is used for indicating whether to occur the ECC decoding error. The bit0 indicates the occurrence of the error for 1st 128byte data, bit1 for 2nd 128byte data, bit3 for 3rd 128 byte data and bit4 for 4th 128byte data
4 (dec_end0) 5 (dec_end0) 6 (dec_end0) 7 (dec_end0) 15:8
0 = progressing 1 = decoding end
Each bit is used for indicating whether to end ECC decoding operation, bit4 for 1st 128byte data, bit5 for 2nd 128byte data, bit6 for 3rd 128 byte data and bit7 for 4th 128byte data Not used
Data Register (FMDATARDWRn) The initial value is 0x00. The width is 16bit. There are 8 registers. These registers are used to store data transmitted or received. CPU have to write the data when the bit[8] of thisregisteris high in write mode. In read mode, CPU have to read the data from this register after checking that the bit[9] or bit[10] is high. At first, User check the bit[10[ after checking bit[9]. Then check those bits in turn.
X16, X8 512byte FMCDATARDWR0 ~7
10/13
S3C49F8X MultiMediaCard CONTROLLER
Syndrome Data output Register (FMSYNDOUTRWn) The initial value is 0x00. There are 4 registers whose width is 16bit. The syndrome data generated from ECC encoder in write mode enter to thess registers.
FMCSYNDOUTRW0 FMCSYNDOUTRW1 FMCSYNDOUTRW2 FMCSYNDOUTRW3 1st 128byte data syndrome data(2byte) 2nd 128byte data syndrome data 3rd 128byte data syndrome data 4th 128byte data syndrome data
To transfer these value to external FM, at first, CPU read these register. After that, CPU write these data to FMDATARDWRn. The way of transfer is same to normal
Syndrome Data input Register (FMSYNDINRWn) The initial value is 0x00. There are 4 register whose width is 16bit. Before read operation in ECC mode, CPU have to write the syndrome data to these register in just order. If the read operation is finished after writing syndrome data, User can the occurrence of error by checking dec_status register.
FMCSYNDINRW0 FMCSYNDINRW1 FMCSYNDINRW2 FMCSYNDINRW3 1st 128byte data syndrome data(2byte) 2nd 128byte data syndrome data 3rd 128byte data syndrome data 4th 128byte data syndrome data
ECC Decoding Result Register (FMDEC_RESULT) The initial value is 0xFFFF. There are 4 register whose width is 16bit.
FMDEC_RESULT0 FMDEC_RESULT1 FMDEC_RESULT2 FMDEC_RESULT3 The result of 1st 128byte data decoding(2byte) The result of 2nd 128byte data decoding The result of 3rd 128byte data decoding The result of 4th 128byte data decoding
11/13
S3C49F8X MultiMediaCard CONTROLLER
Flash Density Register (FMDENSITY) After reading Flash ID, CPU have to set the density register.
BIT 0 1 2 3 4 15:5 FUNCTION Below 256M Bit 512M bit 1G Bit 2G Bit 4G Bit Not used
Flash Controller FMC (FMTEST) The state of fsm in FMC is written in this register..
BIT 4:0 15:5 FSM `0' FUNCTION
* The Flash type and command supported. ( Vcc=2.7 ~ 3.6V, Organization = x8, x16)
Density (bits) 64M Function Read1 Read2 Read ID Reset Page Program Block Erase Status Read Read1 Read2 Read ID Reset Page Program Block Erase Status Read Read1 Read2 Read ID Reset Page Program Block Erase Status Read Copy-back Command Sets 1'st cycle 2'nd cycle 00h/01h 50h 90h FFh 80h 10h 60h D0h 70h 00h/01h 50h 90h FFh 80h 10h 60h D0h 70h 00h/01h 50h 90h FFh 80h 10h 60h D0h 70h 00h 8Ah 3'rd cycle E6h ID
128M
73h
256M
75h
12/13
S3C49F8X MultiMediaCard CONTROLLER
512M (single chip)
512M (Double chip)
1G (single chip)
1G (Double chip)
2G (single,Double chip)
4G (Double chip)
Read1 Read2 Read ID Reset Page Program Block Erase Status Read Copy-back Read1 Read2 Read ID Reset Page Program Block Erase Status Read Copy-back Read Read for copy-back Read ID Reset Page Program Cache Program Copy-back program Block Erase Random input Random output Read Status Read1 Read2 Read ID Reset Page Program Block Erase Status Read Copy-back Read Read for copy-back Read ID Reset Page Program Cache Program Copy-back program Block Erase Random input Random output Read Status Read Read for copy-back Read ID Reset Page Program Cache Program Copy-back program Block Erase Random input Random output Read Status
00h/01h 50h 90h FFh 80h 60h 70h 00h 00h/01h 50h 90h FFh 80h 60h 70h 00h 00h 00h 90h FFh 80h 80h 85h 60h 85h 05h 70h 00h/01h 50h 90h FFh 80h 60h 70h 00h 00h 00h 90h FFh 80h 80h 85h 60h 85h 05h 70h 00h 00h 90h FFh 80h 80h 85h 60h 85h 05h 70h
76h
10h D0h 8Ah 10h 76h
10h D0h 8Ah 30h 35h 10h 15h 10h D0h E0h 79h F1h
10h D0h 8Ah 30h 35h 10h 15h 10h D0h E0h 30h 35h 10h 15h 10h D0h E0h DCh 10h DAh
13/13
SECURE DIGITAL CARD INTERFACE (SDCI)
OVERVIEW
The Secure Digital Card Interface (SDCI) can interface for SD memory card and MultiMedia Card(MMC).
FEATURES
Supports MultiMediaCard Specification Version 3.1 Supports SD Memory Card Specification Version 1.0 Cards Clock Rate up to System Clock(PCLK) Divided by 2 16 words (64 bytes) FIFO (depth 16) for data Transmit 8 words (32 bytes) FIFO (depth 8) for data Receive CRC7 & CRC16 Generator/Checker Normal, and DMA Data Transfer Mode Support for Block and Multi-block Data Read and Write 1bit/4bit(wide bus) Mode switch support Can Be Directly Connected to the AMBA Peripheral Bus (APB) Version 2.0
1
BLOCK DIAGRAM
PCLK PRESETn PSELSDCI PENABLE PWRITE PADDR[7:2] PWDATA[31:0] PRDATA[31:0]
APB I/F
CMD Control
command_output shift register response_input
CRC7
CLOCK Control
clock_output
Tx FIFO
DAT Control
shift register dat_output[3:0] dat_input[3:0]
Rx FIFO
CRC16
d_nreq d_nack
DMA Control
2
Pin Description
Pin Name System Signals PCLK PRESETn APB Signals PSELSDCI PENABLE PWRITE PADDR PWADDR PRADDR External Signal wp_dect_input response_input dat0_input dat1_input dat2_input dat3_input clk_output command_output 1 1 1 1 1 1 1 1 I I I I I I O O O O O O O O O O O Write protect pin input Response input(CMD) Data0 input(DAT0) Data1 input(DAT1) Data2 input(DAT2) Data3 input(DAT3) Clock output(SDCLK) Command output(CMD) Command output enable Data0 output(DAT0) Data0 output enable Data1 output(DAT1) Data1 output enable Data2 output(DAT2) Data2 output enable Data3 output(DAT3) Data3 output enable 1 1 1 6 32 32 I I I I I O Selection on APB Enable in APB Write/Read in APB Address in APB Write data in APB Read data in APB 1 1 I I clock reset Width I/O Description
command_enable 1 dat0_output dat0_enable dat1_output dat1_enable dat2_output dat2_enable dat3_output dat3_enable DMA relative Signal d_nack d_nreq 1 1 1 1 1 1 1 1 1 1
I O
DMA request signal DMA acknowledge signal
3
SDCI Operation
A serial clock line is synchronized with the command and 4 data lines for shifting and sampling of the information. Making the appropriate bit settings to the SDCI_CTRL register depends on the transmission frequency.
SDCI Configuration 1. After a hardware reset, by default, the SDCI pins are deselected and the user must configure the gpio controller to assign PIOs to SDCI peripheral functions. For details, refer to the gpio datasheet.
CMD Path Programming -Operation of broadcast commands (bc, bcr) and addressed commands (ac) 1. Write the argument value to SDCI_ARG register. 2. Write the command information to SDCI_CMD register. - Confirm the ready of command transmission when the specific flag of SDCI_STA[0]. 3. Write the command start bit to SDCI_CMD register. 4. Check the status of SDCI command operation. - Command transmission is in progress, the SDCI_STA[1] is set. - Command transmission is completed, the SDCI_STA[2] is set. - Response reception is in progress, the SDCI_STA[3] is set. - Response reception is completed, the SDCI_STA[4] is set. 5. Check the Status of response - If command response time-out error occur, the SDCI_STA[16] is set. - If response end bit error occur, the SDCI_STA[17] is set. - If response index error occur, the SDCI_STA[18] is set. - If response CRC error occur, the SDCI_STA[19] is set. 6. Check the Card Response, read from SDCI_RESP3~0 register. 7. Clear the corresponding flag of the SDCI_STA register by write the SDCI_STAC register.
DAT path programming (not use DMA) -Operation of addressed data transfer commands (adtc) 1. Write the Data block length to the SDCI_DCTRL register. 2. FIFO reset by writing the SDCI_DCTRL register. 3. Do CMD path Programming 4. Write the Data transmission start bit to SDCI_DCTRL[5:4] register(only data write operation).
4
5. When Write Operation, Write Tx data to SDCI_TXRX register while TxFIFO is available by checking SDCI_STA[13:12]. 6. When Read Operation, Read Rx data to SDCI_TXRX register while RxFIFO is available by checking SDCI_STA[11:10]. 7. Check the status of SDCI data operation. - Data transmission/reception is in progress, the SDCI_STA[5] is set. - Data block transmission/reception is completed, the SDCI_STA[6] is set - Data CRC data transmission/reception is completed, the SDCI_STA[7] is set. - CRC status token reception is completed, the SDCI_STA[8] is set, only write command. - Card busy state, the SDCI_STA[9] is set. 8. Check the Status of data transfer - If write data CRC status token has error, set the SDCI_STA[23] is set, CRC status token value is set SDCI_STA[22:10]. - If read data CRC error occur, set the SDCI_STA[24] is set. - If read data end bit error occur, set the SDCI_STA[28:25] are set. 9. Clear the corresponding flag of the SDCI_STA register by write the SDCI_STAC register. 10. If Multiple data block transfer, repeat 4~9.
DAT path programming (using DMA) 1. Configure SDCI as DMA mode, control register set in DMA module. 2. Write the Data block length to the SDCI_DCTRL register. 3. FIFO reset by writing the SDCI_DCTRL register. 4. Do CMD path Programming 5. Write the Data Transmission start bit to SDCI_DCTRL[5:4] register(only data write operation). 6. The SDCI requests DMA service. 7. DMA transmits data to the SDCI as DMA configuration. 8. Check the Status of data Transfer. 9. If Multiple data block transfer, repeat 1, 5~8.
Note 1. In case of 136bit response, the CRC error should be detected after receiving exact response data form SDCard or MMC. User should check the CRC of receive response by software. 2. User should check the Read, Write and Erase Time-out error.
5
SDCI Register
Offset 0x00 0x04 0x08 0x0c 0x10 0x14 0x18 0x1c 0x20 0x24 0x28 0x2c 0x30 SDCI_RESP0 SDCI_RESP1 SDCI_RESP2 SDCI_RESP3 SDCI_TXRX 32bit 32bit 32bit 32bit 32bit Read Read Read Read Read/Write SDCI_STAC SDCI_STA 32bit 32bit Write Read Register Name SDCI_CTRL SDCI_DCTRL SDCI_CMD SDCI_ARG Width 32bit 32bit 32bit 32bit Read/Write Read/Write Read/Write Read/Write Read/Write Register name Control Register Data Control Register Command Register Argument Register Reserved Status Clear Register Status Register Reserved Response0 Register Response1 Register Response2 Register Response3 Register Data Register 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x8000_1400 Initial Value 0x0000_0000 0x0200_0000 0x0000_0000 0x0000_0000
SDCI Control (SDCI_CTRL) Register Bit 31:16 15:8 Name Reserved CLKDIV Select the SDCLK 0000_0001 0000_0010 0000_0100 0000_1000 0001_0000 0010_0000 0100_0000 1000_0000 ELSE 7:6 5 Reserved DMA_REQ_CON Select DMA request condition, only Read Command 0 1 4 L_ENDIAN DMA request when Receive FIFO is not empty. DMA request when Receive FIFO is full. SDCLK = PCLK/2 SDCLK = PCLK/4 SDCLK = PCLK/8 SDCLK = PCLK/16 SDCLK = PCLK/32 SDCLK = PCLK/64 SDCLK = PCLK/128 SDCLK = PCLK/256 Reserved Description
Select Endian
6
0 1 3 DMAEN
Big endian Little endian
DMA enable 0 1 DMA disable DMA enable
2
BUS_WIDTH
Select the SDCard bus width. Only use SDCard (CARD_TYPE == 1'b0) 0 1 1bit data bus 4bit data bus
1
CARD_TYPE
Select the card type 0 1 SD Card MM Card
0
SDCIEN
SDCI block enable 0 1 Disable the SDCI Enable then SDCI
SDCI Data Control (SDCI_DCTRL) Register Bit 31:16 15:6 5:4 Name BLK_LEN Reserved TRCONT Start the data transfer, automatically cleared. Only write command (CMD_CLASS ==2'b11). 00 01 1x 3:2 1 Reserved RXFIFORST Reset the receive FIFO. 0 1 0 TXFIFIRST No effect Reset the Receive FIFO No effect Data Transmission Start Reserved Description Determine the data block size (unit : byte)
Reset the transmit FIFO. 0 1 No effect Reset the Transmit FIFO
SDCI Command (SDCI_CMD) Register Bit Name Description
7
31
CMDSTR
Start the command transfer, automatically cleared. Only writable when SDCI_SR[0] = 1. 0 1 No effect Command transmit start
30:21 20
Reserved NCR_NID Select the clock cycle command to response. 0 1 NCR (64 clock cycle) NID (5 clock cycle)
19
RES_SIZE
Select the response size 0 1 48 bit size response 136 bit size response
18:16
RES_CLASS
Select response class 000 001 010 011 100 101 110 111 No Response R1, R1b R2 R3 R4 R5 R6 Reserved
15:9 8
Reserved CMD_TYPE Select the command type 0 1 General command Application command
7:6
CMD_CLASS
Select the command class 00 01 10 11 Broadcast commands Addressed commands Addressed data transfer commands - read command Addressed data transfer commands - write command
Caution : Use CMD13 during read/write operation, CMD_CLASS value must maintain the existing value. 5:0 CMD_NUM Set the command number
SDCI Argument (SDCI_ARG) Register Bit Name Description
8
31:0
ARGUMENT
Set the argument value
SDCI STATUS Clear (SDCI_STAC) Register Bit 31:29 28 Name Reserved CLR_RD_DATENDE3 Clear RD_DATENDE3 at SDCI_SR 0 1 27 CLR_RD_DATENDE2 No effect Clear the RD_DATEMDE3 bit Description
Clear RD_DATENDE2 at SDCI_SR 0 1 No effect Clear the RD_DATEMDE2 bit
26
CLR_RD_DATENDE1
Clear RD_DATENDE1 at SDCI_SR 0 1 No effect Clear the RD_DATEMDE1 bit
25
CLR_RD_DATENDE0
Clear RD_DATENDE0 at SDCI_SR 0 1 No effect Clear the RD_DATEMDE0 bit
24
CLR_RD_DATCRCE
Clear RD_DATCRCE at SDCI_SR 0 1 No effect Clear the RD_DATCRCE bit
23
CLR_WR_DATCRCE
Clear WR_DATCRCE at SDCI_SR 0 1 No effect Clear the WR_DATCRCE bit
22:20 19
Reserved CLR_RESCRCE Clear RESCRCE at SDCI_SR 0 1 No effect Clear the RESCRCE bit
18
CLR_RESINDE
Clear RESINDE at SDCI_SR 0 1 No effect Clear the RESINDE bit
17
CLR_RESENDE
Clear RESENDE at SDCI_SR 0 1 No effect Clear the RESENDE bit
16
CLR_RESTOUTE
Clear RESTOUTE at SDCR_SR 0 No effect
9
1 15:9 8 Reserved CLR_CRC_STAEND
Clear the RESTOUTE bit
Clear CRC_STAEND at SDCI_SR 0 1 No effect Clear the CRC_STAEND bit
7
CLR_DAT_CRCEND
Clear DAT_CRCEND at SDCI_SR 0 1 No effect Clear the DAT_CRCEND bit
6
CLR_DATEND
Clear DAT_END at SDCI_SR 0 1 No effect Clear the DATEND bit
5 4
Reserved CLR_RESEND Clear RESEND at SDCI_SR 0 1 No effect Clear the RESEND bit
3 2
Reserved CLR_CMDEND Clear CMDEND at SDCI_SR 0 1 No effect Clear the CMDEND bit
1:0
Reserved
SDCI STATUS (SDCI_STA) Register Clear Condition: A : According to the SDCI interface state. C : Clear by write `1' to corresponding bit of SDCI_SCR. Bit Name Description Clear Condition 31 WP_DECT_INPUT WP pin status 0 1 30:29 28 Reserved RD_DATENDE3 Read data end bit error on dat3 0 1 No Read Data End Bit Error of DAT3 occurs Read Data End Bit Error of DAT3 occurs C WP Pin status is Low WP Pin status is High A
10
27
RD_DATENDE2
Read data end bit error on dat2 0 1 No Read Data End Bit Error of DAT2 occurs Read Data End Bit Error of DAT2 occurs
C
26
RD_DATENDE1
Read data end bit error on dat1 0 1 No Read Data End Bit Error of DAT1 occurs Read Data End Bit Error of DAT1 occurs
C
25
RD_DATENDE0
Read data end bit error on dat0 0 1 No Read Data End Bit Error of DAT0 occurs Read Data End Bit Error of DAT0 occurs
C
24
RD_DATCRCE
Read data has CRC error 0 1 No Read Data CRC Error occurs Read Data CRC Error occurs
C
23
WR_DATCRCE
Write data CRC status response has error 0 1 No CRC status Token Error occurs CRC status Token Error occurs
C
22:20
WR_CRC_STATUS
Write data CRC status response value 010 101 111 else Non erroneous transmission Transmission error Card error Reserved
A
19
RESCRCE
Response CRC error. Not valid, when RES_CLASS = 3'001. 0 1 No Response CRC Error occurs Response CRC Error occurs
C
18
RESINDE
Response index error 0 1 No Response Index Error occurs Response Index Error occurs
C
17
RESENDE
Response end bit error 0 1 No Response End Bit Error occurs Response End Bit Error occurs
C
16
RESTOUTE
Response timeout error (Ncr, Nid) 0 No Command to Response timeout error occurs 1 Command to Response timeout error occurs
C
15:14
Reserved
11
13
TX_FIFO_FULL
Tx FIFO full 0 1 Transmit FIFO is not full Transmit FIFO is full
A
12
TX_FIFO_EMPTY
Tx FIFO empty 0 1 Transmit FIFO is not empty Transmit FIFO is empty
A
11
RX_FIFO_FULL
Rx FIFO full 0 1 Receive FIFO is not full Receive FIFO is full
A
10
RX_FIFO_EMPTY
Rx FIFO empty 0 1 Receive FIFO is not empty Receive FIFO is empty
A
9
DAT_BUSY
Data line busy 0 1 card is not busy card is busy
A
This status is direct connected inverted DAT0 of Card. 8 CRC_STAEND Write data CRC status token receive end 0 1 7 DAT_CRCEND CRC status token reception is not ended CRC status token reception is ended C C
Data CRC transmit/receive end 0 1 CRC transmission/reception is not ended CRC transmission/reception is ended
6
DATEND
Data transmit/receive end 0 1 Data transmission/reception is not ended Data transmission/reception is ended
C
5
DATPRO
Data transfer in progress 0 1 Data transmission/reception is not in
A
progress Data transmission/reception is in progress
4
RESEND
Response receive end 0 1 Response reception is not ended Response reception is ended
C
3
RESPRO
Response receive in progress 0 Response reception is not in progress
A
12
1 2 CMDEND
Response reception is in progress C
Command transfer end 0 1 Command transmission is not ended Command transmission is ended
1
CMDPRO
Command transfer in progress 0 1 Command transmission is not in progress Command transmission is in progress
A
0
CMDRDY
Command ready 0 1 Command transfer is not ready Command transfer is ready (SDCI_CMD, SDCI_ARG set complete)
A
SDCI Response3 (SDCI_RESP3) Register Bit 31:0 Name RESPONSE3 Description The RES_SIZE determines the value RES_SIZE 0 1 RESPONSE3 32'h0000_0000 response[127:96]
SDCI Response2 (SDCI_RESP2) Register Bit 31:0 Name RESPONSE2 Description The RES_SIZE determines the value RES_SIZE 0 1 RESPONSE2 32'h0000_0000 response[95:64]
SDCI Response1 (SDCI_RESP1) Register Bit 31:0 Name RESPONSE1 Description The RES_SIZE determines the value RES_SIZE 0 1 RESPONSE1 32'h0000_0000 response[63:32]
13
SDCI Response0 (SDCI_RESP0) Register Bit 31:0 Name RESPONSE0 Description The RES_SIZE determines the value RES_SIZE 0 1 RESPONSE0 response[39:8] response[31:0]
SDCI Data (SDCI_TXRX) Register Bit 31:0 Name SDCI_TXRX Description Data buffer for transmit/receive
NOTE: If data is not aligned to word(4byte), SDCI_TXRX register value is following table(big_endian). When Data read
write data 4n+1 byte 4n+2 byte 4n+3 byte SDCI_TXRX[31:24] Write data[7:0] Write data[7:0] Write data[7:0] SDCI_TXRX[13:16] stuff bits Write data[15:8] Write data[15:8] SDCI_TXRX[15:8] stuff bits stuff bits Write data[23:16] SDCI_TXRX[7:0] stuff bits stuff bits stuff bits
When Data write
read data 4n+1 byte 4n+2 byte 4n+3 byte SDCI_TXRX[31:24] 0x00 0x00 0x00 SDCI_TXRX[13:16] 0x00 0x00 Read data[7:0] SDCI_TXRX[15:8] 0x00 Read data[7:0] Read data[15:8] SDCI_TXRX[7:0] Read data[7:0] Read data[15:8] Read data[23:16]
14
S5L840F
MEMORY STICK HOST CONTROLLER
15
OVERVIEW
* * * * * * * * 16-bit access
MEMORY STICK HOST CONTROLLER
Protocol is started by writing to the command register from the CPU Data is requested by DMA or Interrupt to the CPU when entering the data period RDY timeout period can be set by the number of serial clock Interrupt can also be output to the CPU when a timeout occurs CRC can be turned off during test mode Built-in 4-bit parallel port The output from FIFO is little endian
FEATURE * * * * * * * * Built-in 8-byte (4-word) FIFO buffers for transmit and receive respectively Built-in CRC circuit Transfer clock up to 80 MHz (Exnternal input. When using the SONY C5MX-HB-T library.) DMA supported Automatic command execution (can be turned on/off) when an INT from the Memory Stick is detected MagicGate supported Approx. 8K gates (When using the SONY C5MX-HB-T library) All registers are described positive edge flip flop (for SCAN)
15-1
MEMORY STICK HOST CONTROLLER
S5L840F
BLOCK DIAGRAM
APB Interface DACK DREQ APB Interface Memory Stick Core
BS SCLKO SDIR SDIO_OUT PO[3:0] SDIO_IN PI[3:0] SCLKI Memory Stick Interface
I/O DMA Interface
Prescaler
Figure 15-1. Memory Stick Host Controller Block Diagram
REGISTERS
PRESCALER CONTROL REGISTER(MSPRE) Register MSPRE Address 3C600000H R/W R/W Description Prescaler Register Reset Value 32 bits
MSPRE CLK_EN
Bit [8]
Description SCLK (XSCLK) output or not 0 = Disable the SCLK (XSCLK) output 1 = Enable the SCLK (XSCLK) output Prescale register to generate the SCLK (XSCLK) from the main clock. SCLK [Hz] = {main clock [Hz] / (MS_PRE + 1)} / 2
Initial State 0h
PRESCALE
[7:0]
0h
15-2
S5L840F
MEMORY STICK HOST CONTROLLER
INTERRUPT ENABLE REGISTER(MSINTEN) Register MSINTEN Address 3C600004H R/W R/W Description Interrupt Enable Register Reset Value 32 bits
MSINTEN CORE_INT_STAT
Bit [12]
Description Interrupt generated by the memory stick host controller. Writing one clears this flag. User should write one to this field and read the MSINT register to deactivate the interrupt signal from the memory stick host controller. The sequence is not important. RBE interrupt status. Writing one clears this flag and deactivates the interrupt. RBF interrupt status. Writing one clears this flag and deactivates the interrupt. TBE interrupt status. Writing one clears this flag and deactivates the interrupt. TBF interrupt status. Writing one clears this flag and deactivates the interrupt. Interrupt enable/disable for the RBE. 0 = Disable the interrupt from RBE 1 = Enable the interrupt from RBE
Initial State 0h
RBE_INT_STAT RBF_INT_STAT TBE_INT_STAT TBF_INT_STAT RBE_INT_EN
[11] [10] [9] [8] [3]
1h 0h 1h 0h 0h
RBF_INT_EN
[2]
Interrupt enable/disable for the RBF. 0 = Disable the interrupt from RBF 1 = Enable the interrupt from RBF
0h
TBE_INT_EN
[1]
Interrupt enable/disable for the TBE. 0 = Disable the interrupt from TBE 1 = Enable the interrupt from TBE
0h
TBF_INT_EN
[0]
Interrupt enable/disable for the TBF. 0 = Disable the interrupt from TBF 1 = Enable the interrupt from TBF
0h
15-3
MEMORY STICK HOST CONTROLLER
S5L840F
COMMAND REGISTER(MSCMD) Register MSCMD Address 3C601000H R/W R/W Description Command Register Reset Value 32 bits
ADCPARA PID
Bit [15:12] Packet ID
Description Writing to Command register starts the protocol. CRC16bit is transfered during the data period even if the data size is 0. PID command is disabled if the data size is 0 and the NOCRC bit of the Control register 1 is 1. Data cannot be written to the Command register when the RDY bit of the Interrupt Control and Data register is 0. (While the protocol is executing.)
Initial State 0h
DATA_SIZE
[9:0]
Data size for each transfer. The PID determines the value.
0h
15-4
S5L840F
MEMORY STICK HOST CONTROLLER
CONTROL/STATUS REGISTER(MSCTRLSTAT) Register MSCTRLSTAT Address 3C601004H R/W R/W Description Control/Status Register Reset Value 32 bits
MSCTRLSTAT RST
Bit [15] Internal reset 0 = Nothing 1 = Internal reset
Description
Initial State 0h
Reserved SIEN
[14] [13]
Reserved to 0 Serial interface enable 0 = Disable the serial interface 1 = Enable the serial interface
0h 0h
Reserved NOCRC
[12] [11]
Reserved to 0. Data is transmitted/received without adding a CRC (16bit) at the end of the data. Normally this bit is set to zero during the operation. 0 = Enable the CRC 1 = Disable the CRC
0h 0h
BSYCNT
[10:8] RDY timeout time setting (serial clock count). This field is set to the maximum BSY timeout time (BSYCNT x 4 + 2) to wait until the RDY signal is output from the memory stick. RDY timeout error detection is not performed when BSYCNT = 0. Initial value is 05h (22 SCLK).
05h
INT
[7]
Indicates the interrupt status 0 = When an interrupt condition is not generated 1 = When an interrupt condition is generated
0h
DRQ
[6]
Indicates DMA request status 0 = When data is not requested 1 = When data is requested
0h
RBE
[3]
Receive buffer empty. 0 = The receive data buffer is not empty 1 = The receive data buffer is empty
1h
RBF
[2]
Receive buffer full. 0 = The receive data buffer is not full 1 = The receive data buffer is full
0h
TBE
[1]
Transmit buffer empty. 0 = The transmit data buffer is not empty 1 = The transmit data buffer is empty
1h
TBF
[0]
Transmit buffer full. 0 = The transmit data buffer is not full 1 = The transmit data buffer is full
0h
15-5
MEMORY STICK HOST CONTROLLER
S5L840F
OPERATION PERFORMED DURING RESET Operations when RST is "1". A value of "1" should be maintained for the RST bit for system clock 2 clocks and SCLKI 2 clocks and then must be returned to "0" in order to perform reset in sync with the clock. If the software-reset operation is executed, the following condition is set. Register operation (Status after RST = 1 and immediately after RST = 0) MSCMD register = 0x00000000 MSCTRLSTAT register = 0x0000050a MSFIFO register = 0x00000000 MSINT register = 0x00000080 MSPP register = 0x00000000 MSCTRL2 register = 0x00000000 MSACD register = 0x00007001 Output signal BS (bus state) SDIO_OUT (SDIO output) SCLKO (memory stick clock) INT nDRQ (DMA request)
= low level = low level = low level = low level = high level
Internal Operation - The Transmit/Receive Data Buffers are cleared - TBE, RBE = 1 - TBF, RBF = 0 - PO = 0 The executing protocol is terminated.
RECEIVE/TRANSMIT DATA BUFFER(MSFIFO) Register MSFIFO Address 3C601008H R/W R/W Description Receie/Transmit Register Reset Value 32 bits
MSFIFO RDATA_BUF TDATA_BUF
Bit [15:0] [15:0] Data buffer for receive
Description - When RBE is one, invalid data is read. Data buffer for transmit - When TBF is one, invalid data is ignored.
Initial State 0h 0h
15-6
S5L840F
MEMORY STICK HOST CONTROLLER
INTERRUPT CONTROL/DATA REGISTER(MSINT) Register MSINT Address 3C60100cH R/W R/W Description Interrupt Control/Data Register Reset Value 32 bits
MSINT INTEN
Bit [15] XINT interrupt enable
Description 0 = XINT interrupt signal output is disabled. 1 = XINT interrupt signal output is enabled.
Initial State 0h
DRQSL PINEN
[14] [13]
0 = XINT output is disabled during data transfer request. 1 = XINT output is enabled during data transfer request. 0 = XINT output is disabled by the change of the value in the XPI[3:0]. 1 = XINT output is enabled by the change of the value in XPI[3:0]. Protocol status 0 = Protocol with the memory stick is not ended. 1 = Protocol with the memory stick is ended. This flag is cleared to zero when writing to the Command register.
0h 0h
RDY
[7]
1h
SIF
[6]
Serial interface interrupt 0 = Serial I/F does not receive an interrupt 1 = Serial I/F receives an interrupt. An interrupt signal is output separately from RDY interrupt.
0h
DRQ
[5]
DMA request 0 = XDRQ (DMA request) is not requested. 1 = When XDRQ (DMA request) output is requested and DRQSL bit is 1.
0h
PIN
[4]
Parallel port input change 0 = Parallel inputs are not changed. 1 = When parallel inputs are changed and PINEN is 1.
0h
CRC
[1]
CRC error 0 = No CRC error occurs. 1 = CRC error occurs. Cleared to zero when data is written to command register (MSCMD). BS output is set to zero, RDY becomes to one, and an interrupt signal is generated.
0h
TOE
[0]
Time out error 0 = No time out error occurs 1 = BSY timeout error occurs Cleared to zero when data is written to the command register (MSCMD) RDY becomes to one and an interrupt signal is output
0h
15-7
MEMORY STICK HOST CONTROLLER
S5L840F
PARALLEL PORT CONTROL/DATA REGISTER(MSPP) Register MSPP Address 3C601010H R/W R/W Description Parallel Port Control/Data Register Reset Value 32 bits
MSPP PIEN
Bit [15:12] Parallel port input enable
Description 0 = Parallel port inputs are disabled 1 = Parallel port inputs are enabled
Initial State 0h
POEN
[11:8]
Parallel port output enable 0 = Parallel port outputs are disabled 1 = Parallel port outputs are enabled
0h
XPIN
[7:4]
Parallel port input data - XPIN[n] is 1 when the PIn pin is low level and 0 when high level. - It takes 32 SCLK cycles for a value from the parallel input pin PI[3:0] to be reflected at the XPIN[3:0]
0h
POUT
[3:0]
Parallel port output data - High level is output when the POUT[n] is set to 1 - Low level is output when the POUT[n] is set to 0
0h
CONTROL REGISTER 2(MSCTRL2) Register MSCTRL2 Address 3C601014H R/W R/W Description Control Register 2 Reset Value 32 bits
MSCTRL2 ACD
Bit [15] Auto command enable
Description 0 = Disable the auto command 1 = Enable the auto command after an interrupt is detected. This flag is automatically cleared to zero after Auto Command processing is ended.
Initial State 0h
RED
[14]
Edge selection for data loading 0 = Serial data is loaded at the rising edge of the clock 1 = Serial data is loaded at the falling edge of the clock
0h
Auto Command is a function used to automatically execute the GET_INT or READ_REG on the host interface. With this function, the interrupt signal from the Memory Stick is detected and the command set in the ACD Command Register is executed. When CRC error or TOE occurs, the Auto Command processing is terminated without performing ACD and an interrupt signal is generated.
15-8
S5L840F
MEMORY STICK HOST CONTROLLER
ACD COMMAND REGISTER(MSACD) Register MSACD Address 3C601018H R/W R/W Description ACD Command Register Reset Value 32 bits
MSACD APID ADATA_SIZE
Bit [15:12] [9:0]
Description PID code (Transport Protocol Command) Data size for each transfer. The PID determines the value.
Initial State 7h 1h
Auto Command is a function used to automatically execute the GET_INT or READ_REG on the host interface. With this function, the interrupt signal from the Memory Stick is detected and the command set in the ACD Command Register is executed.
15-9
MEMORY STICK HOST CONTROLLER
S5L840F
NOTES
15-10
S5L840F
USB DEVICE
16
OVERVIEW
-
USB DEVICE CONTROLLER
Universal Serial Bus (USB) device controller is designed to provide a high performance full speed function controller solution with DMA interface. USB device controller allows bilk transfer with DMA, interrupt transfer and control transfer
USB device controller support : Full speed USB device controller compatible with the USB specification version 1.1 DMA interface for bulk transfer Four endpoint with FIFO EP0 : 16 bytes (Register) EP1 : 64 bytes IN/OUT FIFO EP2 : 64 X 2 bytes IN/OUT FIFO EP3 : 64 X 2 bytes IN/OUT FIFO Integrated USB Transceiver
FEATURE * * * * * * * Fully compliant with USB Specification Version 1.1 Full speed (12Mbps) device Integrated USB Transceiver Supports control, interrupt, Isochronous and bulk transfer Four endpoints with FIFO Supports DMA interface for receive and transmit bulk endpoint. (EP1, EP2 and EP3) Support suspend and remote wakeup function.
19-1
USB DEVICE
S5L840F
BLOCK DIAGRAM
APB
interface DP
SIU
USB Transcei ver
DM
SIE
APB and DMA Interface
ACK[2:0] REQ[2:0]
GFI
FIFO
Figure -1. USB Device Controller Block Diagram
USB DEVICE CONTROLLER SPECIAL REGISTERS
This section describes detailed functionalities about register sets of USB device controller. All special function register is byte-accessible. Common indexed registers depend on INDEX register(INDEX_REG) value. For example if you want to write EP0 CSR register, you must write `0X00' on the INDEX_REG before writing IN_CSR1 register.
16-2
S5L840F
USB DEVICE
Register FUNC_ADDR_REG PWR_MNGNT_REG EP_INT_REG USB_INT_REG EP_INT_EN_REG USB_INT_EN_REG FRAME_NUM1_REG FRAME_NUM2_REG INDEX_REG DMA_EN_REG EP0_FIFO_REG EP1_FIFO_REG EP2_FIFO_REG EP3_FIFO_REG MAXP_REG
Address NON INDEXED REGISTER
Description
3D100000h Function Address Register 3D100010h Power Management Register 3D100020h Endpoint Interrupt Register 3D100060h USB Interrupt Register 3D100070h Endpoint Interrupt Enable Register 3D1000B0h USB Interrupt Enable Register 3D1000C0h Frame Number 1 Register 3D1000D0h Frame Number 2 Register 3D1000E0h Index Register 3D1000F0h DMA Enable Register 3D100200h Endpoint0 FIFO Register 3D100210h Endpoint1 FIFO Register 3D100220h Endpoint2 FIFO Register 3D100230h Endpoint3 FIFO Register COMMON INDEXED REGISTERS 3D100130h Endpoint MAX packet Register IN INDEXED REGISTERS EP In Control Status Register1/ EP0 Control Status Register
IN_CSR1_REG/EP0_CSR IN_CSR2_REG OUT_CSR1_REG OUT_CSR2_REG OUT_WRT_CNT1 OUT_WRT_CNT2
3D100110h
3D100120h EP In Control Status Register2 OUT INDEX REGISTERS 3D100140h EP Out Control Status Register1 3D100150h EP Out Control Status Register2 3D100160h EP Out Write Count Register1 3D100170h EP Out Write Count Register2
16-3
USB DEVICE
S5L840F
FUNCTION ADDRESS REGISTER (FUNC_ADDR_REG) This register maintains the USB device controller address assigned by the host. The MCU writes the value received through a SET_ADDRESS descriptor to this register. This address is used for the next token. Register FUNC_ADDR_REG Address 0X3D100000 R/W R/W Description Function address register Reset Value 0x00
Symbol ADDR_UPDATE FUNCTION_ADDR
Bit [7] [6:0]
MCU R/ SET R/W
USB R/
Description
Reset Value 0
Set by the MCU whenever if updates the FUNC_ADDR field in the register. This bit will CLEAR be cleared by USB when DATA_END bit in EP0_CSR register. R The MCU writes the address to these bits
00
16-4
S5L840F
USB DEVICE
POWER MANAGEMENT REGISTER (PWR_MNGNT_REG) This register is used for suspend, resume and reset signaling. Register PWR_MNGNT_REG Symbol Address 0X3D100010 Bit MCU R/W R/W USB Description Power management register Description Used for ISO mode only. If set, GFI waits for a SOF token to set IN_PKT_RDY even though a packet to send is already loaded by MCU. If an IN token is received before a SOF token, then a zero length data packet will be sent. Reset Value 0X00 Reset Value
ISO_UPDATE
[7]
R/W
R
0
Reserved USB_RESET
[6:4] [3] R Set by the USB if reset signaling is received from the host. This bit remains set as long as reset signaling persists on the bus. Set by the MCU for MCU Resume. The USB R/ generates the resume signaling during 10ms, CLEAR if this bit is set in suspend mode. Set by USB automatically when the device SET/ enter into suspend mode. CLEAR It is cleared under the following conditions: 1) The MCU clears the MCU_RESUME bit by Suspend mode enable control bit 0 = Disable (default) R The device will not enter suspend mode 1 = Enable suspend mode SET 0
MCU_RESUME
[2]
R/W
SUSPEND_MODE
[1]
R
0
SUSPEND_EN
[0]
R/W
0
16-5
USB DEVICE
S5L840F
INTERRUPT REGISTER1 (EP_INT_REG) The USB core has two interrupt registers. These registers act as status registers for the MCU when it is interrupted. The bits are cleared by writing a `1'(not `0') to each bit that was set. Once the MCU is interrupted. MCU should read the contents of interrupt-related registers and write back to clear the contents if it is necessary. Register EP_INT_REG Register Reserved Address 0X3D100020 Bit [8:4] MCU R/W R/W USB Description EP interrupt pending / clear register Description Reset Value 0X00 Reset Value
For BULK/INTERRUPT IN endpoints : Set by the USB under the following conditions: 1. IN_PKT_RDY bit is cleared 2. FIFO is flushed 3. SENT_STALL set For BULK/INTERRUPT OUT endpoints : Set by the USB under the following conditions: 1. Sets OUT_PKT_RDY bit 2. Sets SENT_STALL bit 3. For ISO IN endpoints : Set by the USB under the following conditions: 1. UNDER_RUN bit is set 2. IN_PKT_RDY bit is cleared 3. FIFO is flushed Note : Condition 1 and 2 are mutually exclusive For ISO OUT endpoints : Set by the USB under the following conditions: 1. OUT_PKT_RDY bit is set 2. OVER RUN bit is set Note : Condition 1 and 2 are mutually exclusive
R/ EP1~EP3 [3:1] CLEAR SET
0
16-6
S5L840F
USB DEVICE
EP0 Interrupt
[0]
R/ CLEAR
SET
Correspond to endpoint 0 interrupt. Set by the USB under the following conditions: 1. OUT_PKT_RDY bit is set. 2. IN_PKT_RDY bit is cleared. 3. SENT_STALL bit is set. 4. SETUP_END bit is set. 5. DATA_END bit is cleared. (it indicates the end of control transfer)
0
16-7
USB DEVICE
S5L840F
INTERRUPT REGISTER2 ( USB_INT_REG) Register USB_INT_REG Symbol USB RESET Interrupt Address 0X3D100060 Bit [2] MCU R/ CLEAR R/W R/W USB SET Description USB interrupt pending/clear register Description Set by the USB when it receives reset signaling Set by the USB when it receives resume signaling, while in Suspend mode. If the resume occurs due to a USB reset, then the MCU is first interrupted with a RESUME interrupt. Once the clocks resume and the SE0 condition persists for 3ms, USB RESET interrupt will be asserted. Set by the USB when it receives suspend signalizing. The bit is set whenever there is no activity for 3ms on the bus. Thus, if the MCU does not stop the clock after the first suspend interrupt, it will continue to be interrupted every 3ms as long as there is no activity on the USB bus By default, this interrupt is disabled. Reset Value 0X00 Reset Value 0
RESUME Interrupt
[1]
R/ CLEAR
SET
SUSPEND Interrupt
[0]
R/ CLEAR
SET
0
Note : If the RESET interrupt is occurred, all USB device registers should be re-configured.
16-8
S5L840F
USB DEVICE
INTERRUPT ENABLE REGISTER (EP_INT_EN_REG/USB_INT_EN_REG) Corresponding to each interrupt register. The USB device controller also has two interrupt enable registers (except resume interrupt enable). By default usb reset interrupt is enabled. If bit = 0, the interrupt is disabled. If bit = 1, the interrupt is enabled. Register EP_INT_EN_REG Symbol EP3_INT_EN EP2_INT_EN EP1_INT_EN EP0_INT_EN Address 0X3D100070 Bit [3] [2] [1] [0] MCU R/W R/W R/W R/W R/W R/W USB R R R R Description Determine which interrupt is enabled Description EP3 interrupt enable bit 0 = interrupt disable, 1 = enable EP2 interrupt enable bit 0 = interrupt disable, 1 = enable EP1 interrupt enable bit 0 = interrupt disable, 1 = enable EP0 interrupt enable bit 0 = interrupt disable, 1 = enable Description Determine which interrupt is enabled Description Reset interrupt enable bit 0 = interrupt disable, 1 = enable Suspend interrupt enable bit 0 = interrupt disable, 1 = enable Reset Value 0XFF Reset Value 1 1 1 1
Register USB_INT_EN_REG Symbol RESET_INT_EN Reserved SUSPEND_INT_EN
Address 0X3D1000B0 Bit [2] [1] [0] R/W MCU R/W
R/W R/W USB R
Reset Value 0X04 Reset Value 1 0
R
0
16-9
USB DEVICE
S5L840F
FRAME NUMBER REGISTER (FRAME_NUM1_REG/FRAME_NUM2_REG) When the host transfer USB packets, each Start Of Frame(SOF) packet includes a frame number. The USB device controller catches this frame number and loads it into this register automatically.
Register FRAME_NUM1_REG Symbol FRAME_NUM1
Address 0X3D1000C0 Bit [7:0] MCU R
R/W R USB W
Description Frame number lower byte register Description Frame number lower byte value
Reset Value 00 Reset Value 00
Register FRAME_NUM2_REG Symbol FRAME_NUM2
Address 0X3D1000D0 Bit [7:0] MCU R
R/W R USB W
Description Frame number higher byte register Description Frame number higher byte value
Reset Value 00 Reset Value 00
16-10
S5L840F
USB DEVICE
DMA TRANSFER ENABLE REGISTER (DMA_EN_REG) These registers maintain the number of bytes in the packet as the number is unloaded by the MCU Register DMA_EN_REG Symbol EP3_DMA_ENABLE Address 0X3D1000F0 Bit [3] MCU R/W R/W R/W USB R Description DMA transfer enable register Description Endpoint 3 DMA transfer enable 0 : DMA disable 1 : DMA enable Endpoint 2 DMA transfer enable 0 : DMA disable 1 : DMA enable Endpoint 1 DMA transfer enable 0 : DMA disable 1 : DMA enable Reset Value 00 Reset Value 00
EP2_DMA_ENABLE
[2]
R/W
R
00
EP1_DMA_ENABLE Reserved
[1] [0]
R/W
R
00
16-11
USB DEVICE
S5L840F
INDEX REGISTER (INDEX_REG) The INDEX register is used to indicate certain endpoint registers effectively. The MCU can access the endpoint register (MAXP_REG, IN_CSR1_REG, IN_CSR2_REG, OUT_CSR1_REG, OUT_CSR2_REG, OUT_WRT_CNT1_REG and OUT_WRT_CNT2_REG) for an endpoint inside the core using the INDEX register.
Register INDEX_REG Symbol INDEX
Address 0X3D1000E0 Bit [7:0] MCU R/W
R/W R/W USB R
Description Register index register Description Indicate a certain endpoint
Reset Value 00 Reset Value 00
16-12
S5L840F
USB DEVICE
ENDPOINT0 CONTROL STATUS REGISTER (EP0_CSR) This register has the control and status bits for Endpoint0. Since a control transaction is involved with both IN and OUT tokens, there is only one CSR register, mapped to the IN CSR1 register. (share IN1_CSR and can access by writing index register "0" and read/write IN1_CSR) Register EP0_CSR Symbol SERVICED_SETUP_ END SERVICED_OUT_PK T_RDY Address 0X3D100110 Bit [7] [6] MCU R/W R/W USB Description Endpoint 0 status register Description The MCU should write a "1" to this bit to clear SETUP_END. The MCU should write a "1" to this bit to clear OUT_PKT_RDY. MCU should write a "1" to this bit at the same time it clears OUT_PKT_RDY, if it decodes and invalid token. 0 = Finish the STALL condition 1 = The USB issues a STALL and shake to the current control transfer Set by the USB when a control transfer ends before DATA_END is set. When the USB sets this bit, an interrupt is generated to the MCU. When such a condition occurs, the USB flushes the FIFO and invalidates MCU access to the FIFO. Set by the MCU on the conditions below : 1. After loading the last packet of data into the FIFO, at the same time IN_PKT_RDY is set. 2. While it clears OUT_PKT_RDY after unloading the last packet of data. 3. For a zero length data phase. Set by the USB if a control transaction is stopped due to a protocol violation. An interrupt is generated when this bit is set. The MCU should write "0" to clear this bit. Set by the MCU after writing a packet of data into EP0 FIFO. The USB clears this bit once the packet has been successfully sent to the clears this bit, so as the MCU to load the next packet. For a zero length data phase, the MCU sets DATA_END at the same time. Set by the USB once a valid token is written to the FIFO. An interrupt is generated when the USB sets this bit. The MCU clears this bit by writing a "1" to the SERVICED_OUT_ PKT_RDY bit Reset Value 00 Reset Value 0 0
CLEAR CLEAR CLEAR CLEAR
SEND_STALL
[5]
R/W
CLEAR
0
SETUP_END
[4]
R
SET
0
DATA_END
[3]
SET/ R
CLEAR
0
SENT_STALL
[2]
CLEAR /R
SET
0
IN_PKT_RDY
[1]
SET/R
CLEAR
0
OUT_PKT_RDY
[0]
R
SET
0
16-13
USB DEVICE
S5L840F
ENDPOINT IN CONTROL STATUS 1 REGISTER (IN_CSR1_REG) Register IN_CSR1_CSR Symbol Reserved CLR_DATA_TOGGL E Address 0X3D100110 Bit [7] MCU R/W R/W USB Description IN Endpoint control status 1 register Description Reset Value 00 Reset Value
[6]
SENT_STALL
[5]
SEND_STALL
[4]
FIFO_FLUSH
[3]
UNDER_RUN
[2]
FIFO_NOT_EMPTY
[1]
Used in Set-up procedure. 0 : There are alternation of DATA0 and R R DATA1 1 : The data toggle bit is cleared and PID in packet will maintain DATA0 Set by the USB when an IN token issues a STALL handshake, after the MCU sets R/ SET SEND_STALL bit to start STALL CLEAR handshaking. When the USB issues a STALL handshake, IN_PKT_RDY is cleared 0 : The MCU clears this bit to finish the STALL condition. W/R R 1 : The MCU issues a STALL handshake to the USB. Set by the MCU if it intends to flush the packet in Input-related FIFO. This bit is cleared by the USB when the FIFO is flushed. The MCU is interrupted when this happens. If a token is in process, the USB R/W CLEAR waits until the transmission is complete before FIFO flushing. If two packets are loaded into the FIFO, only first packet(The packet is intended to be sent to the host) is IN_PKT_RDY bit is cleared Valid only For ISO mode Set by the USB when in ISO mode, an IN token is received and the IN_PKT_RDY bit R/ is not set. Set CLEAR The USB sends a zero length data packet for such conditions, and the next packet that is loaded into the FIFO is flushed. This bit is cleared by writing 0. Indicates there is at least one packet of data in FIFO Bit[0] = 0, Bit[1] = 0 : No packet in the FIFO Bit[0] = 1, Bit[1] = 0 : 1 packet in the FIFO R Set (when FIFO size is 2X MAXP) Bit[0] = 1, Bit[1] = 1 : 2 packet in the FIFO (when FIFO size is 2X MAXP) or Bit[0] = 1, Bit[1] = 1 : 1 packet in the FIFO (when FIFO size is MAXP)
0
0
0
0
0
0
16-14
S5L840F
USB DEVICE
IN_PKT_RDY
[0]
R/SET
Set by the MCU after writing a packet of data into the FIFO. The USB clears this bit once the packet has been successfully sent to the host. An interrupt is generated when the USB CLEAR clears this bit, so the MCU can load the next packet. While this bit is set, the MCU will not be able to write to the FIFO. If the MCU sets SEND_STALL bit, this bit can not be set.
0
ENDPOINT IN CONTROL STATUS 2 REGISTER (IN_CSR2_REG) Register IN_CSR2_CSR Symbol Address 0X3D100120 Bit MCU R/W R/W USB Description IN Endpoint control status 2 register Description If set, whenever the MCU writes MAXP data, IN_PKT_RDY will automatically be set by the core without any intervention from MCU. If the MCU writes less than MAXP data, IN_PKT_RDY bit has to be set by the MCU. Used only for endpoints whose transfer type is programmable. 1 : Configures endpoint to ISO mode 0 : Configures endpoint to Bulk mode Used only for endpoints whose direction is programmable. 1 : Configures endpoint direction as IN 0 : Configures endpoint direction an OUT This bit is used only for endpoints whose interface has DMA. 1 : DMA enable 0 : DMA disable Reset Value 20 Reset Value
AUTO_SET
[7]
R/W
R
0
ISO
[6]
R/W
R
0
MODE_IN
[5]
R/W
R
1
DMA_MODE Reserved
[4] [3:0]
W/R
R
0 0
16-15
USB DEVICE
S5L840F
ENDPOINT OUT CONTROL STATUS 1 REGISTER (OUT_CSR1_REG) Register OUT_CSR1_CSR Symbol CLR_DATA_TOGGL E Address 0X3D100140 Bit [7] MCU R/W R/W USB Description OUT Endpoint control status 1 register Reset Value 00 Reset Value 0
SENT_STALL
[6]
SEND_STALL
[5]
FIFO_FLUSH
[4]
DATA_ERROR
[3]
OVER_RUN
[2]
Description When the MCU writes a 1 to this bit, the R SET data toggle sequence bit si reset to DATA0 Set by the USB when an OUT token is ended with a STALL handshake. The USB R/ issues a stall handshake to the host if it SET CLEAR sends more than MAXP data for the OUT_TOKEN, the MCU clears this bit by writing 0. 0 : The MCU clears this bit to end the STALL condition handshake, IN_PKT_RDY is cleared R/W R 1 : The MCU issues a STALL handshake to the USB. The MCU clears this bit to end the STALL condition handshake, IN_PKT_RDY is cleared. The MCU writes a 1 to flush the FIFO. This bit can be set only when OUT_PKT_RDY R/W CLEAR (D0) is set. The packet due to be unloaded by the MCU will be flushed. Valid only in ISO mode This bit should be sampled with OUT_PKT_RDY. When set, it indicates the data packet due to be unloaded by the MCU has an error(either R R/W bit stuffing or CRC). If two packets are loaded into the FIFO, and the second packet has an error, then this bit gets set only after the first packet is unloaded. This bit is automatically cleared when OUT_PKT_RDY gets cleared. Valid only in ISO mode. R/ This bit is set if the core is not able to load R/W CLEAR an OUT ISO token into the FIFO. MCU clears this bit by writing 0. Indicate no more packets can be accepted Bit[0] = 0, Bit[1] = 0 : No packet in the FIFO Bit[0] = 1, Bit[1] = 0 : 1 packet in the FIFO (when FIFO size is 2X MAXP) Bit[0] = 1, Bit[1] = 1 : 2 packet in the FIFO (when FIFO size is 2X MAXP) or Bit[0] = 1, Bit[1] = 1 : 1 packet in the FIFO (when FIFO size is MAXP)
0
0
0
0
0
FIFO_FULL
[1]
R
R/W
0
16-16
S5L840F
USB DEVICE
OUT_PKT_RDY
[0]
R/ CLEAR
SET
Set by the USB after it has loaded a packet of data into the FIFO. Once the MCU reads the packet from FIFO, this bit should be cleared by MCU (write a "0")
ENDPOINT OUT CONTROL STATUS 2 REGISTER (OUT_CSR2_REG) Register OUT_CSR2_CSR Symbol AUTO_CLR Address 0X3D100150 Bit [7] MCU R/W R/W R/W USB R Description OUT Endpoint control status 2 register Description If the MCU is set, whenever the MCU reads data from the OUT FIFO, OUT_PKT_RDY will automatically be cleared by the logic without any intervention from the MCU Determine endpoint transfer type. 0 : Configures endpoint to Bulk mode 1 : Configures endpoint to ISO mode Default = 0 Reset Value 00 Reset Value 0
ISO Reserved
[6] [5:0]
R/W R
R R
0
16-17
USB DEVICE
S5L840F
ENDPOINT FIFO REGISTER (EPn_FIFO_REG) Register EP0_FIFO EP1_FIFO EP2_FIFO EP3_FIFO Address 0X3D100200 0X3D100210 0X3D100220 0X3D100230 R/W R/W R/W R/W R/W Description Endpoint0 FIFO register Endpoint1 FIFO register Endpoint2 FIFO register Endpoint3 FIFO register Reset Value XX XX XX XX
Symbol FIFO_DATA
Bit [7:0]
MCU R/W
USB R/W
Description FIFO data value
Reset Value XX
16-18
S5L840F
USB DEVICE
MAX PACKET REGISGER (MAXP_REG) Register MAXP_REG Symbol MAXP Address 0X3D100130 Bit [7:0] MCU R/W R/W R/W USB R Description Endpoint MAX packet register Description 0000_0000 : MAXP = 8 (default value) 0000_0010 : MAXP = 16 (endpoint 0) 0000_1000 : MAXP = 64 (endpoint 1,2,3) Reset Value 00 Reset Value 00
16-19
USB DEVICE
S5L840F
ENDPOINT OUT WRITE COUNT REGISGER (OUT_WRT_CNT1/OUT_WRT_CNT2) These registers maintain the number of bytes in the packet as the number is unloaded by the MCU Register OUT_WRT_CNT1 Symbol OUT_CNT_LOW Address 0X3D100160 Bit [7:0] MCU R R/W R/W USB W Description Endpoint out write count register1 Description Lower byte of write count Reset Value 00 Reset Value 00
Register OUT_WRT_CNT2 Symbol OUT_CNT_HIGH
Address 0X3D100170 Bit [7:0] MCU R
R/W R/W USB W
Description Endpoint out write count register1 Description Higher byte of write count
Reset Value 00 Reset Value 00
16-20
Chapter 17. IIS(Tx/Rx) module
The IIS bus transmits PCM audio data to external DAC and receives PCM audio data from external ADC. To minimize the number of pins required and to keep wiring simple, a 3-line serial bus which consists of a data line for time-multiplexed two-channel data(left/right), a word select line and a clock line is used. In S5L840F, IIS bus has 6 data lines(one for reception and 5 for transmission), 2 word select lines and 2 clock lines(one for reception and the other for transmission). IIS has two modes for data transfer. In transmission mode, IIS module makes a request for PCM audio data to IODMA module and IODMA module brings audio data decoded by ADM from SDRAM. In reception mode, IIS module gets audio data from external source and stores them into SDRAM by requesting DMA to IODMA module. 5 data lines are synchronized with 1 word select line and 1 clock line for transmission mode and 1 data line is synchronized with 1 word select line and 1 clock line for reception mode. In IIS bus, the chip which generates the bit clock is called master. Either transmitter or receiver of audio data has to generate the bit clock and word select clock as a master since they use the same clock signal for data transfer. S5L840F acts only as a master in IIS bus, that is, always provides two clock signals(bit clock and word select clock) for a slave even when it receives audio data.
Feature
2 data transfer modes - transmission, reception DMA mode transfer only 5 x 24-bit buffers for Transmission and 1 x 24-bit buffer for reception 16/20/24 bit data per channel Up to 10 channels for transmission and 2 channels for reception MSB-first or LSB-first transfer mode IIS, left-justified and right-justified format compatible Burst transfer mode, which makes Tx buffer filled by burst length in one request. Master mode only Programmable frequency divider for serial bit clock LRCK polarity change at both posedge and negedge of serial bit clock 32, 48, 64fs(sampling frequency) serial bit clock per frame ( left channel + right channel ) 256, 384, 512fs master clock(DAC clock)
S5L840F
IIS
Block Diagram
SDO (5 ch) TxSCLKO TxLRCKO BRFC DATA BUFFER RxSFTR RxCHNC MCLK RxSCLKG SDI (1 ch) RxSCLKO RxLRCKO
MCLK
TxSCLKG TxCHNC
TxSFTR
ADDR DATA CNTL PCLK
CDCLK
Fig 1. IIS Block Diagram BRFC : register bank, APB interface, finite state machine for DMA request TxSCLKG, RxSCLKG : generation of serial bit clock for Tx and Rx, respectively DATA BUFFER : 24-bit data buffer for Tx and Rx TxCHNC, RxCHNC : generation of control signals which connect data buffer with shift register, data alignment depending on various data transfer mode TxSFTR, RxSFTR : shift register which transfers parallel data serially
2
S5L840F
IIS
Pin Description
Pin Name PCLK PRESETn APB Interface PSEL PENABLE PWRITE PADDR PWDATA PRDATA IIS Interface MCLK CDCLK TXSCLKO TXLRCKO SDO0 SDO1 SDO2 SDO3 SDO4 RXSCLKO RXLRCKO SDI DMA Request DMAREQn DMAACKn Width 1 1 1 1 1 4 24 32 1 1 1 1 1 1 1 1 1 1 1 1 2 2 I/O I I I I I I I O I O O O O O O O O O O I O I Global clock Global reset Selection in APB Enable in APB Write/Read in APB Address in APB Write data in APB Read data in APB Audio main clock External DAC clock Serial bit clock for transmission Word select signal for transmission Audio data output Audio data output Audio data output Audio data output Audio data output Serial bit clock for reception Word select signal for reception Audio data input DMA request signal [Tx, Rx] DMA acknowledge signal [Tx, Rx] Description
3
S5L840F
IIS
Registers
Name I2SCLKCON I2STXCON I2STXCOM I2STXDB0 I2SRXCON I2SRXCOM I2SRXDB I2SSTATUS Width 32 32 32 32 32 32 32 32 Address (virtual) 0x3ca0 0000(0x39 4000) 0x3ca0 0004(0x39 4004) 0x3ca0 0008(0x39 4008) 0x3ca0 0010(0x39 4010) 0x3ca0 0030(0x39 4030) 0x3ca0 0034(0x39 4034) 0x3ca0 0038(0x39 4038) 0x3ca0 003c(0x39 403c) R/W R/W R/W R/W W R/W R/W R R Description Clock Control Register Tx configuration Register Tx command Register Tx data buffer Rx configuration Register Rx command Register Rx data buffer status register Reset 0x0000 0002 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 000D
I2S Clock Control Register (I2SCLKCON) 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 1 16 0 0
I2SCLKCON
Bit [31:2] Reserved
Description
Initial State 0
I2S clock down ready
(read only)
I2S power on
[1] [0]
0 = clock-down not ready 0 = power off
1 = clock-down ready 1 = power on
1 0
4
S5L840F
I2S Tx Configuration Register (I2STXCON) 31 15 0 30 14 1 29 13 1 28 12 0 27 11 0 26 10 0 25 9 1 24 8 1 23 7 0 22 6 1 21 5 0 20 4 0 19 3 1
IIS
18 2 0
17 1 0
16 0 1
I2STXCON
Bit [31:19]
Description Reserved Burst length(BL) selection Burst Length = ( BL[2:0] + 1 ) 0 = SCLK falling edge 1 = SCLK rising edge 0x = IIS (basic format) 10 = Left justified 11 = Right justified 0 = MSB first (Normal audio interface mode) 1 = LSB first 0 = Left Channel for Low polarity 1 = Left Channel for High polarity SCLK = MCLK / {(3-bit value +1) * 2} Reserved ( always recognized as zero ) 00 = 16 bit 10 = 24 bit 00 = 32 fs 10 = 64 fs 01 = 20 bit 11 = N/A 01 = 48 fs 11 = N/A
Initial State 0 0 0 00
Burst mode LRCK change Audio format polarity interface
[18:16] [15] [14:13]
MSB first or LSB firstIn Serial Interface Left/Right channel polarity ( LRCK ) 4-bit scaler for SCLK generation Serial Data Bit per Channel Bit Clock per Frame (Frame = Left + Right) Channel index
[12] [11] [10:8] [7] [6:5] [4:3] [2:0]
0 0 000 0 00 00 0
Channel index=number of channels / 2 (<=5 )
5
S5L840F
I2S TX Command Register (I2STXCOM) 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 1
IIS
18 2 1
17 1 1
16 0 0
I2STXCOM
Bit [31:4] Reserved
Description
Initial State 0 0 0 0 0
Tx enable select2 I2S interface enable
[3] [2] [1] [0]
0 = No transfer 1 = Transmit Mode On 0 = I2S interface disable (stop) 1 = I2S interface enable (start) 0 = DMA request disable 1 = DMA request enable 0 = Channel not idle ( LRCK On ) 1 = Channel idle ( LRCK Off )
DMA service request enable
Channel Command Idle
I2S Data Buffer Register (I2STXDB) 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 23 22 6 21 5 20 4 19 3 18 2 17 1 16 0
8 7 DATA
I2STXDB I2S Transmit Data
Bit [31:0]
Description Transmit Data to DAC
Initial State 0
6
S5L840F
I2S RX Configuration Register (I2SRXCON) 31 15 30 14 29 13 28 12 0 27 11 1 26 10 1 25 9 0 24 8 0 23 7 0 22 6 1 21 5 1 20 4 0 19 3 1
IIS
18 2 0
17 1 0
16 0 1
I2SRXCON
Bit [31:13] Reserved
Description
Initial State 0 0 0 0 0 0 0 0 0
LRCK change Audio format
polarity interface
[12] [11:10] [9] [8] [7:5] [4] [3:2] [1:0]
MSB first or LSB first in Serial Interface Left/Right polarity channel
0 = SCLK falling edge 1 = SCLK rising edge 0x = IIS (basic format) 10 = Left justified 11 = Right justified 0 = MSB first (Normal audio interface mode) 1 = LSB first 0 = Left Channel for Low polarity 1 = Left Channel for High polarity SCLK = MCLK / {(3-bit value+1) * 2} Reserved ( always recognized as zero ) 00 = 16 bit 10 = 24 bit 00 = 32 fs 10 = 64 fs 01 = 20 bit 11 = N/A 01 = 48 fs 11 = N/A
4-bit scaler for SCLK generation Serial Data Bit per Channel Bit Clock per Frame (Frame = Left + Right)
7
S5L840F
I2S Rx Command Register (I2SRXCOM) 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 1
IIS
18 2 1
17 1 1
16 0 0
I2SRXCOM
Bit [31:4] Reserved
Description
Initial State 0 0 0 0 0
Rx enable select I2S interface enable
[3] [2] [1] [0]
0 = No transfer 1 = Receive Mode On 0 = I2S interface disable (stop) 1 = I2S interface enable (start) 0 = DMA Request disable 1 = DMA Request enable 0 = Channel not idle ( LRCK On ) 1 = Channel idle ( LRCK Off )
DMA service request enable
Channel Command Idle
I2S Rx Data Buffer Register (I2SRXDB) 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 22 6 21 5 20 4 19 3 18 2 17 1 16 0
7 DATA
I2SRXDB I2S Receive Data
Bit [31:0]
Description Receive Data from ADC
Initial State 0
8
S5L840F
I2S Status Register (I2SSTATUS) 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 1
I2SSTATUS Bit [31:4] RXDBEMP RXLRIDX TXDBFUL TXLRIDX [3] [2] [1] [0] Description Reserved Rx data buffer state flag
IIS
18 2 1
17 1 0
16 0 1
Initial State 0
0 = not empty
Rx Left/Right channel index
1 = empty 1 = right
1 1 0 1
0 = left channel channel
Tx data buffer state flag
0 = not full
Tx Left/Right channel index
1 = full 1 = right
0 = left channel channel
IIS Operations
IIS Clock Frequency The main clock of IIS(PCLK) is the same as system clock whose frequency is 117MHz. Audio main clock(MCLK) is made by PLL2 and is determined considering sampling frequency of audio data. The relationship between sampling frequency(fs) and audio main clock is shown in Table 1. Serial bit clock(SCLK) is determined depending on MCLK and data bit per channel(Table 2) and is set by the value of configuration register(I2STXCON, I2SRXCON). Word select signal(LRCK) has the same frequency as sampling frequency(fs).
LRCK (fs) MCLK (MHz)
8.000 KHz 256fs 2.048 384fs 3.072 512fs 4.096
11.03 KHz 2.822 4.234 5.645
16.00 KHz 4.096 6.144 8.192
22.05 KHz 5.645 8.467 11.29
32.00 KHz 8.192 12.29 16.38
44.10 KHz 11.29 16.93 22.58
48.00 KHz 12.29 18.43 24.58
64.00 KHz 16.38 24.58 32.77
88.20 KHz 22.58 33.87 45.16
96.0 KHz 24.58 36.86 49.15
Table 1. the frequency of audio main clock
9
S5L840F
Serial bit per channel Serial clock frequency (BCLK) @CODECLK=256fs @CODECLK=384fs @CODECLK=512fs 32fs, 64fs 32fs, 48fs 32fs, 64fs 32fs, 64fs 32fs, 48fs 32fs, 64fs 16-bit 20-bit
IIS
24-bit 32fs, 64fs 32fs, 48fs 32fs, 64fs
Table 2. the frequency of serial bit clock Audio Interface Format
LRCK BCLK IISD
MSB (1st)
LEFT
RIGHT
LEFT
2nd Bit
N-1th Bit
LSB (last)
MSB (1st)
2nd Bit
N-1th Bit
LSB (last)
MSB (1st)
IIS-BUS FORMAT (N=16, 24 or 32)
LRCK BCLK IISD
MSB (1st) 2nd Bit
LEFT
RIGHT
LSB (last)
0
MSB (1st)
2nd Bit
LSB (last)
0
MSB-JUSTIFIED FORMAT (N=16, 24 or 32)
LRCK BCLK IISD
LEFT
RIGHT
0
MSB (1st)
N-1th Bit
LSB (last)
0
MSB (1st)
N-1th Bit
LSB (last)
LSB-JUSTIFIED FORMAT (N=16, 24 or 32)
Fig 2. audio data interface format In S5L840F, IIS module is applicable to various interface format as shown above. IIS-Bus format starts data transfer at the next BCLK clock after word select signal(LRCK) changes the polarity. But MSB-Justified format transfers data from the very clock that LRCK changes the polarity. LSBjustified format completes one channel transfer at the same time as the change of LRCK. If there exists more serial clock bits in one channel than serial data bits, the remaining clock bits are stuffed with zero's in each case.
10
S5L840F
IIS
Depending on register values, MSB of audio data or LSB can be transferred first and data transfer can be synchronized with the rising edge or falling edge of LRCK. Start and Stop Condition To make IIS module active, I2S_power_on bit in I2SCLKCON must be set to `1'. After IIS module becomes active, Setting command register to `0x0000 000E' drives IIS to its function mode. IIS_interface_enable bit in command register decides the generation of serial bit clock(SCLK) and makes IIS bus stop immediately after it is set to `0'. IIS_channel_idle_command bit decides the generation of word select signal(LRCK) and makes IIS transfer one pair datum after it is set to `0' and then makes it stop. Therefore, IIS_interface_enable bit can be used to refresh current SDRAM data and IIS_channel_idle_command bit be used to maintain current SDRAM data. To make IIS inactive, the procedure is as follows. 1. Set I2S_power_on to `0'. 2. Wait until I2S_power_down_ready becomes set to `1'. DMA Data Transfer IIS module gives audio data to MEMORY or gets from MEMORY through IODMA module. Therefore, IIS module sends the request signal to IODMA module for audio data and receives acknowledgement signal after the completion of data transfer. Both request and acknowledgement signal have 2 bits, one for transmission and the other for reception. For transmission, IIS module sends request signal when Tx data buffers are not occupied and receives acknowledgement signal after it receives audio data by burst length. Since IIS module acquires audio data by burst length per request and acknowledgement counter also increases by burst length per request, burst mode bit in I2STXCON must be set with the same burst length as in IODMA module to increase acknowledgement counter correctly. If acknowledgement counter is less than the number of channels, that is, data buffer is not full after one request, IIS module sends request signal until data_buffer_full flag becomes set to `1'. After data_buffer_full flag is set to `1', internal signal which indicates the start of next channel transfers audio data in buffers into Tx shift registers and resets data_buffer_full flag to `0'. For reception, the data buffer is empty at first(buffer_empty flag = `1'). The audio data are received into Rx shift register and is transferred to data buffer with the internal channel_start signal. After the buffer_empty flag becomes set to `0', IIS module sends request signal for Rx to IODMA and then receives acknowledgement signal after audio data in data buffer is read. Data reception is independent of data transmission and therefore the two modes can function simultaneously. Program guide of Rx mode IIS module is consist of IIS RX part and TX part. Each part has IIS interface signals (LRCK, BCK, ADATA). And we support only master mode of IIS Rx. So S5L840F share two pin LRCK, BCK. As this restriction, there is some problem of receiving wrong data. This is a program guide to use Rx mode. 1. DMA channel 0 set (IIS Tx channel) DMABASE0, DMACON0, DMATCNT0, DMACOM0 registers set 2. DMA channel 1 set (IIS Rx channel) DMABASE0, DMACON0, DMATCNT0, DMACOM0 registers set 3. IIS Rx mode set ( you must set Rx mode first and then set Tx mode )
11
S5L840F
I2SRXCON register set 4. IIS Tx mode set I2STXCON register set 5. IIS Rx clock on I2SRXCOM register set 6. IIS Tx clock on I2STXCOM register set
IIS
12
Chapter 18. IIC module
S5L840F has a multi-master IIC-bus serial interface. A dedicated serial data line (SDA) and a serial clock line (SCL) carry information between bus masters and peripheral devices that are connected to the IIC-bus. The SDA and SCL lines are bi-directional. To control multi-master IIC-bus operations, values must be written to the following registers. - Multi-master IIC-bus control register, IICCON - Multi-master IIC-bus control/status register, IICSTAT - Multi-master IIC-bus Tx/Rx data shift register, IICDS - Multi-master IIC-bus address register, IICADD When the IIC-bus is free, the SDA and SCL lines should be both at high level. A high-to-low transition of SDA line initiates a start condition while SCL line remains at high level. A low-to-high transition of SDA line with SCL line high generates a stop condition with SCL line high. The start and stop condition should always be generated by the master devices. A 7-bit address value in the first data transfer, which is put onto the bus after the start condition, determines the slave device that is addressed by the 7-bit address. The 8th bit in the first data transfer determines the direction of the transfer (read or write). Every data onto the SDA line should be eight bits or one byte. The number of bytes that can be transferred during the bus transfer is unlimited. Data is always sent from the MSB bit and acknowledge (ACK) bit should be asserted after one byte transfer.1
FEATURE
Four operation mode - Master transmitter mode - Master receive mode - Slave transmitter mode - Slave receive mode Configurable slave address Operation pending until the interrupt pending flag is cleared by the software
1
This is dependent on the devices. Some other devices, for example EEPROM, need not to generate ACK signals.
S5L840F
IIC
BLOCK DIAGRAM
Address Register Comparator
SCL
IIC-Bus Control Logic
Shift Register SDA 4-bit Prescaler Shift Register IICDS
IICCON
IICSTAT
APB
Fig 1. IIC Block Diagram
PIN DESCRIPTION
Pin Name GCLK PRESETn APB Interface PSEL PENABLE PWRITE PADDR PWDATA PRDATA IIC Interface SCLIN SDAIN SCLOUT SDAOUT Interrupt Interface INTC Width 1 1 1 1 1 6 8 32 1 1 1 1 1 I/O I I I I I I I O I I O O O Global clock Global reset Selection in APB Enable in APB Write/Read in APB Address in APB Write data in APB Read data in APB IIC clock line input IIC data line input IIC clock line output IIC data line output Interrupt Description
GCLK APB clock (main clock) PRESETn Global reset to reset the internal register APB interface signals (psel, penable, pwrite, paddr, pwdata, prdata) AMBA APB interface signals SCLIN
2
S5L840F
IIC clock input line. SDAIN IIC data input line SCLOUT IIC clock output line SDAOUT IIC data output line INTC Interrupt signal.
IIC
REGISTERS
Name IICCON IICSTAT IICADD IICDS Width 32 32 32 32 Address(Virtual) 0x3c90 0000(0x39 2000) 0x3c90 0004(0x39 2004) 0x3c90 0008(0x39 2008) 0x3c90 000c(0x39 200c) R/W R/W R/W R/W R/W Description Control Register Control/Status Register Bus Address Register Transmit/Receive Data Shift Register Reset 0x0000 000x 0x0000 0000 -
3
S5L840F
Multi-Master IIC-Bus Control Register (IICCON) 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3
IIC
18 2
17 1
16 0
Bits 7
Name Acknowledge Generation (ACK_GEN) Tx Clock Source Selection (CKSEL) Tx/Rx Interrupt (INT_EN)
Type R/W
6
R/W
5
R/W
Description Reset IIC-bus acknowledge enable bit 0 Disable 1 Enable 0 In Tx mode, the IICSDA is free in the ack time. In Rx mode, the IICSDA is low in the ack time. Source clock of IIC-bus transmit clock pre-scaler selection bit 0 0 IICCLK = PCLK / 16 1 IICCLK = PCLK / 512 IIC-bus Tx/Rx interrupt enable/disable bit 0 0 Disable 1 Enable IIC-bus Tx/Rx interrupt pending flag. Read Operation 0 No interrupt pending 1 Interrupt is pending. In this condition, the IICSCL is tied to low and the IIC is stopped.
4
Interrupt Pending Flag1 (IRQ)
R/W
0
3:0
Transmit Clock Value (CK_REG)
R/W
Write Operation 0 Nothing occurs 1 Clear the pending condition and resume the operation IIC-bus transmit clock prescaler IIC-bus transmit clock frequency is determined by this 4-bit prescaler value, according to the following formular: Tx clock = IICCLK / (IICCON[3:0] + 1) - Shuld be CK_REG[3:0] > 0
-CK_REG[3:0] 0 SCL SDA 0 . 0 . - Slave Mode CK_SEL, CK_REG Master ? => Slave clock .
1
4
An IIC-bus interrupt occurs When one-byte transmit or receive operation is completed When a general call or a slave address match occurs If bus arbitration fails
S5L840F
Multi-Master IIC-Bus Control/Status Register (IICSTAT) 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3
IIC
18 2
17 1
16 0
Bits 7:6
Name Mode Selection (MODE_SEL)
Type R/W
5
Busy Signal Status/ START-STOP Generation (BB) Serial Output (SOE)
Description IIC-bus master/slave Tx/Rx mode selection 00 Slave receive mode 01 Slave transmit mode 10 Master receive mode 11 Master transmit mode Read Operation: IIC-bus busy signal status bit 0 Not busy 1 Busy Write Operation: START-STOP signal generation 0 STOP signal generation 1 START signal generation IIC-bus data output enable/disable bit 0 Disable Tx/Rx 1 Enable Tx/Rx IIC-bus arbitration procedure status flag 0 Bus arbitration successful 1 Bus arbitration failed during serial I/O IIC-bus address-as-slave status flag 0 When START/STOP condition was detected 1 Received slave address matches the address value in the IICADD IIC-bus address zero status flag 0 When START/STOP condition was detected 1 Received slave address is 00000000b IIC-bus last received bit status flag 0 Last received bit is 0 (ACK was received) 1 Last received bit is 1 (ACK was not received)
Reset 0
R/W
0
4 3
R/W
0 0
Arbitration Status R Flag (LBA) Address-as-slave Status Flag (AAS) R
2
0
1 0
Address Zero Status Flag R (ADDR_ZERO) Last Received Bit R Status Flag (LRB)
0 0
% I2C 1byte ack interrupt . interrupt SCL LOW BUS . % I2C Device default "0" slave address ack Master I2C Slave write
.
5
S5L840F
Multi-Master IIC-Bus Address Register (IICADD) 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 19
IIC
18 2
17 1
16 0
4 3 S_ADDR
Bits 7:1
-
Name Slave Address (S_ADDR)
Type R/W
Description 7-bit slave address. When serial output is disabled, IICADD is writable. Slave address = IICADD[7:1]
Reset -
IICADD Slave Address serial output disable . serial output enable Slave Address Reset "0" .
Multi-Master IIC-Bus Transmit/Receive Register (IICDS) 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 18 2 17 1 16 0
3 DATA
Name Type Description 8-bit data shift register for IIC-bus Tx/Rx operation: Data Shift R/W 7:0 When serial output is enabled, IICDS is writable. (DATA) - Serial Output Enable IICDS . IICDS Unkown SDA .
Bits
Reset -
IIC OPERATION
IIC Clock Frequency PCLK 121.5 MHz CKSEL PCLK / 16 PCLK / 512 CK_REG = 0 7.593 MHz 237 KHz CK_REG = 15 474 KHz 14 KHz
In S5L840F, the main clock is 121.5 MHz. So the available operation frequency of IIC is as shown in the above table. User can adjust the operation frequency by the CK_REG field in the IICCON register. Start and Stop Condition When the IIC-bus interface is inactive, it is usually in Slave mode. In other words, the interface should be in Slave mode before detecting a Start condition on the SDA line (a Start condition can be initiated with a High-to-Low transition of the SDA line while the clock signal of SCL is high). When the interface state is changed to Master mode, a data transfer on the SDA line can be initiated and SCL signal generated.
6
S5L840F
IIC
A Start condition can transfer one-byte serial data over the SDA line, and a Stop condition can terminate the data transfer. A Stop condition is a Low-to-High transition of the SDA line while SCL is high. Start and Stop conditions are always generated by the master. The IIC-bus gets busy when a Start condition is generated. A Stop condition will make the IIC-bus free. When a master initiates a Start condition, it should send a slave address to notify the slave device. One byte of address field consists of a 7-bit address and a 1-bit transfer direction indicator (showing write or read). If bit 8 is 0, it indicates a write operation (transmit operation); if bit 8 is 1, it indicates a request for data read (receive operation). The master will finish the transfer operation by transmitting a Stop condition. If the master wants to continue the data transmission to the bus, it should generate another Start condition as well as a slave address. In this way, the read-write operation can be performed in various formats.
SDA
SDA
SCL
SCL
Start Condition
Stop Condition
Figure 2. Start and Stop Condition
Data Transfer Format Every byte placed on the SDA line should be eight bits in length. The bytes can be unlimitedly transmitted per transfer. The first byte following a Start condition should have the address field. The master can transmit the address field when the IIC-bus is operating in Master mode. Each byte should be followed by an acknowledgement (ACK) bit. The MSB bit of the serial data and addresses are always sent first.
7
S5L840F
IIC
Write Mode Format with 7-bit Addresses S Slave Address 7bits R/W A "0" (Write) DATA(1Byte) AP
Data Transferred (Data + Acknowledge)
Write Mode Format with 10-bit Addresses S Slave Address 1st 7 bits 11110XX R/W A "0" (Write) Slave Address 2nd Byte A DATA AP
Data Transferred (Data + Acknowledge)
Read Mode Format with 7-bit Addresses S Slave Address 7 bits R/W A "1" (Read) DATA AP
Data Transferred (Data + Acknowledge)
Read Mode Format with 10-bit Addresses S Slave Address 1st 7 bits 11110XX R/W A "1" (Read) Slave Address 2nd Byte A rS Slave Address 1st 7 Bits R/W A "1" (Read) DATA AP
Data Transferred (Data + Acknowledge)
NOTES: 1. S : Start, rS: Repeat Start, 2. : From Master to Slave,
P : Stop, A: Acknowledge : From Slave to Master
Figure 3. IIC-Bus Interface Data Format
% restart scl low start restart . scl high start bit 1 write start (scl low) start bit 1 write restart .
8
S5L840F
IIC
SDA MSB Acknowledgement Signal from Receiver Acknowledgement Signal from Receiver
SCL S
1
2
7
8
9 ACK
1
2
9
Byte Complete, Interrupt within Receiver
Clock Line Held Low by receiver and/or transmitter
Figure 4. Data Transfer on the IIC-Bus
Ack Signal Transmission To complete a one-byte transfer operation, the receiver should send an ACK bit to the transmitter. The ACK pulse should occur at the ninth clock of the SCL line. Eight clocks are required for the one-byte data transfer. The master should generate the clock pulse required to transmit the ACK bit. The transmitter should release the SDA line by making the SDA line high when the ACK clock pulse is received. The receiver should also drive the SDA line Low during the ACK clock pulse so that the SDA keeps Low during the high period of the ninth SCL pulse. The ACK bit transmit function can be enabled or disabled by software (IICSTAT). However, the ACK pulse on the ninth clock of SCL is required to complete the one-byte data transfer operation.
Clock to Output
Data Output by Transmitter
Data Output by Receiver
SCL from Master
S Start Condition
1
2
7
8
9
Clock Pulse for Acknowledgment
Figure 5. Acknowledge on the IIC-Bus
9
S5L840F
Read-Write Operation
IIC
In transmitter mode, when the data is transferred, the IIC-bus interface will wait until IIC-bus Data Shift (IICDS) register receives a new data. Before the new data is written to the register, the SCL line should be held low, and then released after it is written. The IIC controller should hold the interrupt to identify the completion of current data transfer. After the CPU receives the interrupt request, it should write a new data into the IICDS register, again. In Receive mode, when a data is received, the IIC-bus interface will wait until IICDS register is read. Before the new data is read out, the SCL line will be held low and then released after it is read. The IIC controller should hold the interrupt to identify the completion of the new data reception. After the CPU receives the interrupt request, it should read the data from the IICDS register.
-Master 7bit Slave 8 bit R/W Slave R/W Transmit or Receive Mode . Master Slave Transmit or Receive .
Bus Arbitration Procedures Arbitration takes place on the SDA line to prevent the contention on the bus between two masters. If a master with a SDA high level detects the other master with a SDA active low level, it will not initiate a data transfer because the current level on the bus does not correspond to its own. The arbitration procedure will be extended until the SDA line turns high. However, when the masters simultaneously lower the SDA line, each master should evaluate whether or not the mastership is allocated to itself. For the purpose of evaluation, each master should detect the address bits. While each master generates the slaver address, it should also detect the address bit on the SDA line because the SDA line is likely to get low rather than to keep high. Assume that one master generates a low as first address bit, while the other master is maintaining high. In this case, both masters will detect low on the bus because the low status is superior to the high status in power. When this happens, low (as the first bit of address) generating master will get the mastership while high (as the first bit of address) generating master should withdraw the mastership. If both masters generate low as the first bit of address, there should be arbitration for the second address bit, again. This arbitration will continue to the end of last address bit. Abort Conditions If a slave receiver cannot acknowledge the confirmation of the slave address, it should hold the level of the SDA line high. In this case, the master should generate a Stop condition and to abort the transfer. If a master receiver is involved in the aborted transfer, it should signal the end of the slave transmit operation by canceling the generation of an ACK after the last data byte received from the slave. The slave transmitter should then release the SDA to allow a master to generate a Stop condition. Configuring IIC-Bus To control the frequency of the serial clock (SCL), the 4-bit prescaler value can be programmed in the IICCON register. The IIC-bus interface address is stored in the IIC-bus address (IICADD) register. (By default, the IIC-bus interface address has an unknown value.)
10
S5L840F
FLOWCHARTS OF OPERATIONS IN EACH MODE
IIC
The following steps must be executed before any IIC Tx/Rx operations.
1) Write own slave address on IICADD register, if needed. 2) Set IICCON register
a) Enable interrupt b) Define SCL period
3) Set IICSTAT to enable Serial Output
START Master Tx mode has been configured. (Write 0xC0 to IICSTAT) Write slave address to IICDS. Write 0xF0 (M/T Start) to IICSTAT. The data of the IICDS is transmitted. ACK period and then interrupt is pending. Y
Stop? N
Write new data transmitted to IICDS. Clear pending bit to resume. The data of the IICDS is shifted to SDA.
Write 0xD0 (M/T Stop) to IICSTAT.
Clear pending bit.
Wait until the stop condition takes effect. END
Figure 6. Operations for Master/Transmitter Mode
11
S5L840F
IIC
START Master Rx mode has been configured. (Write 0x80 to IICSTAT) Write slave address to IICDS. Write 0xB0 (M/R Start) to IICSTAT. The data of the IICDS (slave address) is transmitted. ACK period and then interrupt is pending. Y
Stop? N
Read a new data from IICDS. Clear pending bit to resume.
Write 0x90 (M/R Stop) to IICSTAT.
Clear pending bit.
SDA is shifted to IICDS.
Wait until the stop condition takes effect. END
Figure 7. Operations for Master/Receiver Mode
12
S5L840F
IIC
START Slave Tx mode has been configured. (Write 0x50 to IICSTAT) IIC detects start signal. and, IICDS receives data. IIC compares IICADD and IICDS (the received slave address). N
Matched? Y
The IIC address match interrupt is generated.
Write data to IICDS.
Clear pending bit to resume. Y
Stop? N
The data of the IICDS is shifted to SDA.
END
Interrupt is pending.
Figure 8. Operations for Slave/Transmitter Mode
13
S5L840F
IIC
START Slave Rx mode has been configured. (Write 0x10 to IICSTAT) IIC detects start signal. and, IICDS receives data. IIC compares IICADD and IICDS (the received slave address). N
Matched? Y
The IIC address match interrupt is generated.
Read data to IICDS.
Clear pending bit to resume. Y
Stop? N
SDA is shifted to IICDS.
END
Interrupt is pending.
Figure 9. Operations for Slave/Receiver Mode
14
SPI
Preliminary Spec
Version 0.1 Aug. 29, 2003
Byeong-Woo Jeon Media Player P/T System LSI Division Device Solution Network
S5L840FX
SPI
Contents
SPI .....................................................................................................................................................................
PRELIMINARY SPEC ................................................................................................................................. 1 REVISION HISTORY..................................................................................................................................... 3 OVERVIEW........................................................................................................................................................ 3 FEATURE .......................................................................................................................................................... 4 BLOCK DIAGRAM ............................................................................................................................................. 4 PIN DESCRIPTION ............................................................................................................................................. 5 REGISTERS........................................................................................................................................................ 6 SPI OPERATIONS ............................................................................................................................................ 11
2
S5L840FX
SPI
REVISION HISTORY
Date 2003.08.29 Version Number 0.1 Initial version Update Contents
Overview
SPI(Serial Peripheral Interface) in S5L840FX can transfer serial data with various peripherals. SPI has two 8bit shift registers for transmission and reception, respectively. During an transfer, SPI receives 8bit serial data at the same time as it transmits at a frequency determined by prescaler register setting. If you want only to transmit data through SPI, you may treat the received data as dummy. On the contrary, if you want only to receive data, you should write dummy `0xFF' data to Tx buffer since transmission and reception happen at the same time. There are 4 I/O pins associated with SPI transfer : an SPI clock pin(SCK), an MISO(master_in_slave_out) data pin, an MOSI(master_out_slave_in) data pin and an active low /nSS pin. SCK, MISO and MOSI pins act as inputs or outputs depending on register setting and are stitched in the PAD module using associated signals from SPI module. /nSS input pin indicates that the SPI module is used as a slave by an external master.
3
S5L840FX
SPI
Feature
SPI protocol(Ver. 2.11) compatible 2 8-bit Shift Registers for transmission and reception 10-bit prescaler logic Polling, Interrupt and DMA transfer mode master and slave mode 4 combinations of clock polarity and clock phase
Block Diagram
APB PCLK PRESCALER Master Baud Rate
SPI clock
COUNT Clock
Master Slave
SCK
CPOL CPHA
APB_IF
PIN LOGIC 8-bit data Shift Register Master Slave Slave Master MOSI
INT DMAREQ DMAACK
DMA mode
MISO
INT_DMA Master
Fig 1. SPI Block Diagram APB_IF : register bank, interrupt generation INT_DMA : DMA request PRESCALER : generation of prototype SPI clock from PCLK COUNT : generation of SPI clock depending on clock mode, clock count Shift Register : 2 8-bit shift registers for transmission and reception PIN LOGIC : generation of signals needed to make 3 basic SPI pins
4
S5L840FX
SPI
Pin Description
Pin Name Width 1 PCLK 1 PRESETn APB Interface 1 PSEL 1 PENABLE 1 PWRITE 3 PADDR 12 PWDATA 12 PRDATA SPI Interface 1 MI 1 SI 1 CKI 1 nSSI 1 MO 1 nEN_MO 1 SO 1 nEN_SO 1 CKO 1 nEN_CKO DMA Request & Interrupt 1 nDREQ 1 nDACK 1 INT_SPI I/O I I I I I I I O I I I I O O O O O O O I O Global clock Global reset Selection in APB Enable in APB Write/Read in APB Address in APB Write data in APB Read data in APB Data input for master mode Data input for slave mode Clock input for slave mode Active low signal indicating whether SPI module is slave or not Data output for master mode Data output enable for master mode Data output for slave mode Data output enable for slave mode Clock output for master mode Clock output enable for master mode Active low DMA request signal Active low DMA acknowledgement signal Interrupt of SPI module Description
3 basic SPI pins(MOSI, MISO, SCK) are organized as follows in pad module using signals above.
nEN_MO MO SI nEN_SO SO MI nEN_CKO CKO CKI SCK MISO MOSI
5
S5L840FX
SPI
Registers
Base address : 0x3cd0_0000 (in 32bit), 0x39_a000 (in 24bit) Name SPCLKCON SPCON SPSTA SPPIN SPTDAT SPRDAT SPPRE Width 32 24 32 24 32 24 32 24 32 24 32 24 32 24 Address Base + 00h Base + 04h Base + 08h Base + 0ch Base + 10h Base + 14h Base + 18h R/W R/W R/W R/W R/W R/W R R/W Description Clock Control Register Control Register Status Register Pin Control Register Tx Data Register Rx Data Register Baud Rate Prescaler Register Reset 0x0000 0002 0x0000 0000 0x0000 0001 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000
SPI Clock Control Register (SPCLKCON) 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0
SPCLKCON
Bit [31:2] Reserved
Description
Initial State 0
SPI clock down ready
(read only)
SPI power on
[1] [0]
0 = clock-down not ready 0 = power off
1 = clock-down ready 1 = power on
1 0
6
S5L840FX
SPI Control Register (SPCON) 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3
SPI
18 2
17 1
16 0
SPCON
Bit [31:10] Reserved 0 = interrupt masked 0 = interrupt masked 0 = interrupt masked 0 = Tx DMA
Description
Initial State 0
Interrupt Enable (Data Collision error) Interrupt Enable (Multi Master error) Interrupt Enable (Transfer Ready) DMA direction SPI mode select SPI clock enable Master or Slave mode Clock Polarity Select
[10] [9] [8] [7] [6:5] [4] [3] [2]
1 = interrupt enable 1 = interrupt enable 1 = interrupt enable 1 = Rx DMA
0 0 0 0 00 0 0 0
Determine how SPTDAT/SPRDAT is written/read 00 = polling mode 01 = interrupt mode 10 = DMA mode 11 = reserved SPI clock enable (master) or not (slave) 0 = disable 1 = enable 0 = slave mode 1 = master mode NOTE : In slave mode, set-up time is required for master to initiate Tx/Rx Select an active high or active low clock 0 = active high 1 = active low This bit selects one of two fundamentally different transfer formats. 0 = first clock edge missing 1 = last clock edge missing This bit decides whether receiving data automatically transmits dummy 0xFF data or not. When you only want to receive data, you don't have to transmit dummy 0xFF data if this bit is set. 0 = normal mode 1 = Tx auto garbage data mode
Clock Phase Select
[1]
0
Tx Auto Garbage Data mode enable (TAGD)
[0]
0
7
S5L840FX
SPI Status Register (SPSTA) 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3
SPI
18 2
17 1
16 0
SPSTA
Bit [31:4] Reserved 0 = no interrupt
Description
Initial State 0
1 = interrupt pending 0
Interrupt Status Bit (Data Collision Error)
[3]
( This interrupt is generated if SPTDAT is written or SPRDAT is read while transfer is in progress. This bit can be reset by writing `1' . Writing `0' has no effect. ) 0 = no interrupt 1 = interrupt pending ( This interrupt is generated if nSS signal goes to low while SPI is configured as a master and ENMUL bit of SPPIN register is set. This bit can be reset by writing `1' . Writing `0' has no effect. ) 0 = no interrupt 1 = interrupt pending ( This interrupt is generated if transfer ready flag is high in the state of interrupt mode. This bit can be reset by writing `1'. Writing `0' has no effect. ) This flag indicates that SPTDAT or SPRDAT is ready to transmit or receive. It is automatically cleared by writing data to SPTDAT. 0 = not ready 1 = data Tx/Rx ready
Interrupt Status Bit (Multi Master Error)
[2]
0
Interrupt Status Bit (Transfer Ready)
[1]
0
Transfer Ready Flag (Read only)
[0]
1
8
S5L840FX
SPI Pin Control Register (SPPIN) 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3
SPI
18 2
17 1
16 0
SPPIN
Bit [31:4] Reserved
Description
Initial State 0
nSSI pin enable
[3]
Multi Master Error Detect Enable
[2]
This bit determine whether to use nSSI pin or not 0 = don't use (slave condition : MSTR bit is off) 1 = use (slave condition : MSTR bit is off and nSSI is low) This bit enables Multi Master Error Flag of SPSTA to be set when multi master error occurs. 0 = disable (general purpose) 1 = multi master error detect enable Reserved Determine whether state is kept or released in MOSI when 1 byte transfer is finished. (only master) 0 = release 1 = keep the state
0
0
[1] Master Out Keep [0]
0 0
SPI Tx Data Register (SPTDAT) 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0
SPTDAT
Bit [31:8] Reserved
Description
Initial State 0 0
Tx Data
[7:0]
This field contains the data to be transmitted over SPI channel
9
S5L840FX
SPI RX Data Register (SPRDAT) 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3
SPI
18 2
17 1
16 0
SPRDAT
Bit [31:8] Reserved
Description
Initial State 0 0
Rx Data
[7:0]
This field contains the data to be received over SPI channel
SPI Baud Rate Prescaler (SPPRE) 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0
SPPRE
Bit [31:8] Reserved
Description
Initial State 0 0
Prescaler Value
[9:0]
Determines SPI clock rate with the following equation. Baud Rate = PCLK / ( 2 * ( prescaler value +1 ))
10
S5L840FX
SPI
SPI Operations
SPI Transfer Format SPI has 4 transfer formats depending on CPOL and CPHA values in SPCON register. SPI generates clock only when SPI transfers or receives data. CPHA indcates whether SPICLK has a leading edge of the first clock ( CPHA = 1 ) or trailing edge of the last clock( CPHA = 0 ). CPOL determines the polarity of SPICLK when SPI bus is idle.
Cycle SPICLK MOSI MISO
1
2
3
4
5
6
7
8
MSB MSB
6 6
5 5
4 4
3 3
2 2
1 1
LSB LSB MSB
CPOL= 0 , CPHA = 0 (Format A) Cycle SPICLK MOSI MISO MSB MSB 6 6 5 5 4 4 3 3 2 2 1 1 LSB LSB 1 2 3 4 5 6 7 8
CPOL= 0 , CPHA = 1 (Format B) Cycle SPICLK MOSI MISO MSB MSB 6 6 5 5 4 4 3 3 2 2 1 1 LSB LSB MSB 1 2 3 4 5 6 7 8
CPOL= 1 , CPHA = 0 (Format C) Cycle SPICLK MOSI MISO MSB MSB 6 6 5 5 4 4 3 3 2 2 1 1 LSB LSB MSB 1 2 3 4 5 6 7 8
CPOL= 1 , CPHA = 1 (Format D)
Fig. 1. SPI Transfer Format
11
S5L840FX
SPI Operation
SPI
Using the SPI operation, 8-bit data can be sent to and received from external device simultaneously. A serial clock line synchronizes shifting and sampling of the data on the two serial data line. When SPI acts as a master, transmission frequency can be controlled by setting the appropriate bit to SPRPE register. You can modify its frequency to adjust the baud rate data register value. When SPI acts as a slave, the other master supplies the clock. SPI starts its operation as soon as a byte data is written to SPTDAT register. If 0th bit of SPCON is set, reading SPRDAT register makes data transfer start without needing to write 8'hFF to SPTDAT. Programming Procedure When a byte data is written to the SPTDAT register, SPI starts to transmit data if clock-enable bit and master-slave bit of SPCON reginster are set. To operate SPI module, refer to the following steps. 1. Set Baud Rate Prescaler Register(SPPRE). 2. Set SPCON to configure SPI module properly 3. Set the GPIO pin which acts as nSS of external SPI device to low to make external SPI device slave. 4. To transmit data, check the status of Transfer Ready flag of SPSTA register is high and then write data to SPTDAT. 5. To receive data, if 0th bit of SPCON (TAGD) is inactive, write 8'hFF to SPTDAT register, confirm REDY to set and then read data from SPRDAT register. If TAGD bit is active, confirm REDY to set and then read data from SPRDAT register. In this case, there is no need to write data to SPTDAT. 6. Set the GPIO pin which acts as nSS to high to deactivate external SPI device. Steps for DMA Mode Transmission 1. 2. 3. 4. 5. 6. Configure SPI as DMA mode. The SPI requests DMA service. DMA transmits 1 byte data to the SPI. The SPI transmits data to external SPI module Go to step 2 until DMA count is 0. The SPI is configured as interrupt or polling mode.
Steps for DMA mode Reception 1. 2. 3. 4. 5. 6. 7. 8. Configure SPI as DMA mode and set TAGD bit to high The SPI receives 1 byte data from external SPI module. The SPI requests DMA service. DMA receives the data from the SPI. Write data 8'hFF automatically to SPTDAT. Go to step 4 until DMA count is 0. The SPI is configured as polling mode and TAGD bit is cleared. When REDY flag of SPSTA register is set, read the last byte data.
NOTE : Total received data = DMA TC values + the last datum received in polling mode (step 9) The first received datum is dummy, so user may neglect that.
12
SPDIF
Preliminary Spec
Version 0.1 Aug. 29, 2003
Byeong-Woo Jeon Media Player PT System LSI Division Device Solution Network
S5L840FX
SPDIF
Contents
SPDIF .............................................................................................................................................................. 1
PRELIMINARY SPEC ................................................................................................................................. 1 REVISION HISTORY..................................................................................................................................... 3 OVERVIEW........................................................................................................................................................ 3 FEATURE .......................................................................................................................................................... 3 BLOCK DIAGRAM ............................................................................................................................................. 4 PIN DESCRIPTION ............................................................................................................................................. 5 REGISTERS........................................................................................................................................................ 6 SPDIF OPERATIONS ....................................................................................................................................... 10
2
S5L840FX
SPDIF
REVISION HISTORY
Date 2003.08.29 Version Number 0.1 Initial version Update Contents
Overview
This standard describes a serial, un-directional, self-clocking interface for the interconnection of digital audio equipment for consumer and professional applications. When used in a consumer digital processing environment, the interface is primarily intended to carry stereophonic programs, with a resolution of up to 20 bits per sample, an extension to 24 bits per sample being possible. When used in a broadcasting studio environment, the interface is primarily intended to carry monophonic or stereophonic programs, at a 48kHz sampling frequency and with a resolution of up to 24 bits per sample; it may alternatively be used to carry one or two signals sampled at 32 kHz. In both cases, the clock references and auxiliary information are transmitted along with the program. Provision is also made to allow the interface to carry data related to computer software.
Feature
SPDIF module only supports the consumer application in S5L840FX. Linear PCM up to 24-bit per sample is supported. Non-linear PCM formats such as AC3, MPEG1 and MPEG2 are also supported. 2 x 24-bit buffers which is alternately filled with data
3
S5L840FX
SPDIF
Block Diagram
APB
Apb Interface
audio_if_core
Spdif_tx
out_spdif
spdif
DMA Interface
Clock generator
Fig 1. SPDIF Block Diagram APB interface block : defines register banks to control the driving of SPDIF module and data buffers to store linear or non-linear PCM data. DMA interface block : requests DMA service to IODMA depending on the status of data buffer in APB Interface block Clock Generator block : makes 128fs(sampling frequency) clock used in out_spdif block from system audio clock(MCLK) audio_if_core block : acts as interface block between data buffer and out_spdif block. Finite-state machine controls the flow of PCM data. spdif_tx block : inserts burst preamble and executes zero-stuffing in the nonlinear PCM stream. Linear PCM data are bypassed by spdif_tx module. out_spdif block : makes spdif format. It inserts 4-bit preamble, 16- or 20- or 24-bit data, user-data bit, validity bit, channel status bit and parity bit into the appropriate position of 32-bit word. It modulates each bit to bi-phase format.
4
S5L840FX
SPDIF
Pin Description
Pin Name PCLK i-dac-clock PRESETn APB Interface PSEL PENABLE PWRITE PADDR PWDATA PRDATA SPDIF Interface o-spdif-data 1 O Spdif data output 1 1 1 3 32 32 I I I I I O Selection in APB Enable in APB Write/Read in APB Address in APB Write data in APB Read data in APB Width 1 1 1 I I I I/O Global clock Global audio main clock Global reset Description
DMA Request & Interrupt nDMAREQ nDMAACK spdif-int 1 1 1 O I O Active low DMA request signal Active low DMA acknowledgement signal Interrupt of SPDIF module
5
S5L840FX
SPDIF
Registers
Base address : 0x3cb0_0000 (in 32bit), 0x39_6000 (in 24bit) Name SPDCLKCON SPDCON SPDBSTAS SPDCSTAS SPDDAT SPDCNT Width 32 24 32 24 32 24 32 24 32 24 32 24 Address Base + 00h Base + 04h Base + 08h Base + 0ch Base + 10h Base + 14h R/W R/W R/W R/W R/W W R/W Description Clock Control Register Control Register Burst Status Register Channel Status Register SPDIF Data Buffer Repetition Count Register Reset 0x0000 0002 0x0000 0020 0x0000 0000 0x2000 8000 0x0000 0000 0x0000 0000
SPDIF Clock Control Register (SPDCLKCON) 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0
SPCLKCON
Bit [31:2] Reserved
Description
Initial State 0
SPDIF clock down ready (read only) SPDIF power on
[1] [0]
0 = clock-down not ready 0 = power off
1 = clock-down ready 1 = power on
1 0
6
S5L840FX
SPDIF Control Register (SPDCON) 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3
SPDIF
18 2
17 1
16 0
SPDCON
Bit [31:9] Reserved 0 = not empty
Description
Initial State 0
Data Buffer Empty Flag (read only) Interrupt Status bit Interrupt Enable bit software reset bit Main Audio Frequency PCM Data Size PCM or Stream Clock
[8]
1 = empty
1
[7] [6] [5] [4:3] [2:1] [0]
0 = no interrupt pending 1 = interrupt pending ( Interrupt status bit can be reset by writing `1' to this bit. Writing `0' to interrupt status bit has no effect. ) 0 = interrupt masked 0 = normal operation 00 = 256fs 10 = 512fs 00 = 16 bit 10 = 24 bit 0 = stream 1 = interrupt enable 1 = software reset 01 = 384fs 11 = reserved 01 = 20 bit 11 = reserved 1 = PCM
0 0 0 0 0 0
7
S5L840FX
SPDIF Burst Status Register (SPDBSTAS) 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3
SPDIF
18 2
17 1
16 0
SPDBSTAS Burst Data Length Bit Bitstream number Data Type Dependent Info Error Flag
Bit
Description
Initial State 0 0 0 0 0
[31:16] ES size in bits ( Burst Preamble Pd ) [15:13] Bit_stream_number, shall be set to 0 [12:8] [7] [6:5] Data type dependent information 0 = error flag indicating a valid burst_payload 1 = error flag indicating that the burst payload may contain errors Reserved 0000 = Pause data 0001 = AC-3 0010 = MPEG1 ( layer1 ) 0011 = MPEG1 ( layer2, 3 ), MPEG2-bc 0100 = MPEG2 - extension 0101 = MPEG2 ( layer1 - lsf ) 0110 = MPEG2 ( layer2, layer3 - lsf ) others = Reserved
Compressed Data Type
[4:0]
0
8
S5L840FX
SPDIF Channel Status Register (SPDCSTAS) 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3
SPDIF
18 2
17 1
16 0
SPDCSTAS
Bit [31:30] Reserved
Description
Initial State 0 10
Clock Accuracy
[29:28]
10 = Level I, 50 ppm 00 = Level II, 1000 ppm 01 = Level III, variable pitch shifted 0000 = 44.1 kHz 0100 = 48 kHz 1100 = 32 kHz Bit 20 is LSB Bit 16 is LSB Equipment type CD player = 1000_0000 DAT player = 1100_000L DCC player = 1100_001L Mini disc = 1001_001L (L : information about generation status of the material) 00 = Mode 0 000 = emphasis not indicated 100 = emphasis - CD type 0 = copyright 0 = linear PCM 0 = consumer format format 1 = no copyright 1 = non-linear PCM 1 = professional others = Reserved
Sampling Frequency Channel Number Source Number
[27:24] [23:20] [19:16]
0 0 0
Category Code
[15:8]
80
Channel Status Mode Emphasis Copyright Assertion Audio Sample Word Channel Status Block
[7:6] [5:3] [2] [1] [0]
0 0 0 0 0
9
S5L840FX
SPDIF Data Buffer (SPDDAT) 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3
SPDIF
18 2
17 1
16 0
SPDDAT
Bit [31:24] Reserved
Description
Initial State 0 0
SPDIF Data
[23:0]
PCM or stream data
SPDIF Repetition Count Register (SPDCNT) 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0
SPDCNT
Bit [31:13] Reserved
Description
Initial State 0 0
Stream Count
Repetition
[12:0]
Repetition count according to data type This bit is valid only for stream data.
10
S5L840FX
SPDIF
Data Format of SPDIF
Frame Format A frame is uniquely composed of two sub-frames. The transmission rate of frames corresponds exactly to the source sampling frequency. In the 2-channel operation mode, the samples taken from both channels are transmitted by time multiplexing in consecutive sub-frames. Sub-frames related to channel 1(left or "A" channel in stereophonic operation and primary channel in monophonic operation) normally use preamble M. However, the preamble is changed to preamble B once every 192 frame. This unit composed of 192 frames defines the block structure used to organize the channel status information. Subframes of channel 2(right or "B" in stereophonic operation and secondary channel in monophonic operation) always use preamble W. In the single channel operation mode in a broadcasting studio environment the frame format is identical to the 2-channel mode. Data is carried only in channel 1. In the sub-frames allocated to channel 2, time slot 28(validity flag) shall be set to logical "1"(not valid).
M
Channel1
W
Channel 2
B
Channel 1
W
Channel 2
M
Channel 1
W
Channel 2
Sub-frame Frame 191
Sub-frame Frame 1
Frame 0 Start of Block
11
S5L840FX
Sub-frame Format (IEC 60958)
SPDIF
Each sub-frame is divided into 32 time slot, numbered from 0 to 31. Time slot 0 to 3 carry one of the three permitted preambles. These are used to affect synchronization of sub-frames, frames and blocks. Time slots 4 to 27 carry the audio sample word in linear 2's complement representation. The most significant bit is carried by time slot 27. When a 24-bit coding range is used, the least significant bit is in time slot 4. When a 20-bit coding range is sufficient, the least significant bit is in time slot 8 and time slot 4 to 7 may be used for other application. Under these circumstances, the bits in the time slot 4 to 7 are designated auxiliary sample bits. If the source provides fewer bits than the interface allows(24 or 20), the unused least significant bits shall be set to a logical "0". By this procedure, equipment using different numbers of bits may be connected together. Time slot 28 carries the validity flag associated with the audio sample word. This flag is set to logical "0" if the audio sample is reliable. Time slot 29 carries one bit of the user data associated with the audio channel transmitted in the same sub-frame. The default value of the user bit is logical "0". Time slot 30 carries one bit of the channel status words associated with the audio channel transmitted in the same sub-frame. Time slot 31 carries a parity bit such that time slots 4 to 31 inclusive will carry an even number of ones and an even number of zeros.
0
3
4 L S B Aux
78 L S B Audio sample word
28
31
Sync Preamble
M SVUCP B Validity flag
User data Channel Status Parity bit
Channel Coding To minimize the dc component on the transmission line, to facilitate clock recovery from the data stream and to make the interface insensitive to the polarity of connections, time slots 4 to 31 are encoded in biphase-mark. Each bit to be transmitted is represented by a symbol comprising two consecutive binary states. The first state of a symbol is always different from the second state of the previous symbol. The second state of the symbol is identical to the first if the bit to be transmitted is logical "0", is different from the first if the bit is logical "1".
Clock (twice bit rate)
Source coding
Channel coding (bi-phase mark)
12
S5L840FX
Preamble
SPDIF
Preambles are specific patterns providing synchronization and identification of the sub-frames and blocks. A set of three preambles is used. These preambles are transmitted in the time allocated to four time slots(time slots 0 to 3) and are represented by eight successive states. The first state of the preamble is always different from the second state of the previous symbol. Like bi-phase code, these preambles are dc free and provide clock recovery. They differ in at least two states from any valid biphase sequence. Non-Linear PCM Encoded Source(IEC 61937) The non-linear PCM encoded audio bitstream is transferred using the basic 16-bit data area of the IEC 60958 subframes, i.e. in time slots 12 to 27. Each IEC 60958 frame can transfer 32 bits of the non-PCM data in consumer application mode. When the SPDIF bitstream conveys linear PCM audio, the symbol frequency is 64 times the PCM sampling frequency(32 time slots per PCM sample times two channels). When a non-linear PCM encoded audio bitstream is conveyed by the interface, the symbol frequency shall be 64 times the sampling rate of the encoded audio within that bitstream. But in the case where a non-linear PCM encoded audio bitstream is conveyed by the interface containing audio with low sampling frequency, the symbol frequency shall be 128 times the sampling rate of the encoded audio within that bitstream. Each data burst contains a burst-preamble consisting of four 16-bit words (Pa, Pb, Pc, Pd), followed by the burst-payload which contains data of an encoded audio frame. The burst-preamble consists of four mandatory fields. Pa and Pb represent a synchronization word; Pc gives information about the type of data and some information/control for the receiver; Pd gives the length of the burst-payload, limited to 216(=65,535) bits. The four preamble words are contained in two sequential SPDIF frames. The frame beginning the data-burst contains preamble word Pa in subframe 1 and Pb in subframe 2. The next frame contains Pc in subframe 1 and Pd in subframe 2. When placed into a SPDIF subframe, the MSB of a 16-bit burst-preamble is placed into time slot 27 and the LSB is placed into time slot 12.
Data-burst
Stuffing
Data-burst
Stuffing
Data-burst
Stuffing
Data-burst
...
Pa
Pb
Pc
Pd
Burst-payload
Pa
Pb
Pc
Pd
Repetition period between two data-bursts
13
S5L840FX
SPDIF
SPDIF operation
Since the bit frequency of SPDIF is 128fs(fs : samling frequency), the main clock of SPDIF is made by dividing audio main clock(MCLK) depending on the frequency of MCLK. MCLK is divided by 2 in case of 256fs, by 3 in case of 384fs and by 4 in case of 512fs. SPDIF module in S5L840FX plays the role of transforming audio sample data into the format of SPDIF. To do this, SPDIF module inserts preamble data, channel status data, user data, error check bit and parity bit into the appropriate time slots. Preamble data are fixed in the module and inserted depending on subframe counter. Channel status data are set in the SPDCSTAS register and used by one bit per frame. User data always have zero values. For non-linear PCM data, burst-preamble which consists of Pa, Pb, Pc and Pd must be inserted before burst-payload and zero is stuffed from the end of burst-payload to the repetition count. Pa(=16'hF872) and Pb(=16'h4E1F) is fixed in the module and Pc and Pd is set in the register SPDBSTAS. To stuff zero, the end of burst-payload is calculated from Pd value and repetition count which depends on data type in the preamble Pc is acquired from register SPDCNT. Audio data are justified to the LSB. 16- , 20- or 24-bit PCM data and 16-bit stream data are supported. The unoccupied upper bits of 32-bit word are ignored. Data are fetched through DMA request. When one of two data buffers is empty, DMA service is requested. Audio data stored in the data buffers are transformed into SPDIF format and output to the port. For non-linear PCM data, interrupt is generated after audio data are output up to the value specified in the SPDCNT register. Interrupt makes the registers such as SPDBSTAS and SPDCNT be set to new values when data type of new bitstream is different from the previous one.
14
LCD INTERFACE CONTROLLER
OVERVIEW
LCD Interface controller supports the interface between LCD controller with 6800series (Motorola) and 8080serise(intel).
FEATHER
8/4 bit parallel interface mode(6800/8080). 3 Pin / 4 Pin serial Interface mode. Support multiple frequencies internal clock for high and low speed controller. Contains an 16 bytes FIFO for sending control and data information to the LCD controller. Apply 32 Bits, 16bit and 8bit write APB Bus on FIFO. Contains maskable interrupts.
BLOCK DIAGRAM
APB BUS I/F
APB I/F & Contoller
FIFO
P_Interface
Parallel I/F Out
LCD I/F
PCLK
CLK_GEN
LCD_CLK
S_Interface
Serial I/F
1.
APB I/F & Controller : This block supports the interface with HOST and generate the control signal, interrupt and status.
2.
CLK_GEN : As to the value set in register, this block generate the lcd clock which is used as clock source in this block. (1/2/4/8/16/32/64/128 divider).
3.
FIFO : 9 bits x 16 depth FIFO.
MSB 1bit is used as RS Signal(Command/Data)
LSB 8 bits is used for sending data. Each data is send to P_interface or S_interface block as to control register. 4. P_Interface : This block control the data transfer including control signal in parallel mode. In serial mode, this block is disabled. 5. S_Interface : This block control the data transfer including control signal in serial mode. In parallel mode, this block is disabled.
PIN DESCRIPTION
Width TestMode PCLK PRESETn APB Interface PSEL PENABLE PWRITE PADDR PWDATA PRDATA LCD driver Interface LCD_RST LCD_CSB LCD_RS LCD_RW_WR LCD_E_RD LCD_DB[3:0] LCD_DB[5:4] LCD_DB[6]/SCLK LCD_DB[7]/SDO Interrupt Interface INT_LCD 1 O Interrupt Signal 1 1 1 1 1 4 2 1 1 O O O O O I/O I/) I/O I/O LCD driver reset LCD driver chip select LCD driver register select. Read / Write execution control pin Read / Write execution control pin Bi-directional data bus(8bit mode) Bi-directional data bus(8bit/4bit mode) Bi-directional data bus & SCLK Bi-directional data bus & SDO 1 1 1 4 9 9 I I I I I O Selection in APB Enable in APB Write / Read in APB Address in APB Write data in APB Read data in APB 1 1 1 I/O I I I Description For scan enable signal Global clock Global reset
LCD driver Interface LCD_RST : LCD driver reset signal. LCD_CSB : LCD driver chip select signal. LCD_RS : LCD driver register select signal. RS = 1 : DB0 to DB7 are display data. RS = 0 : DB0 to DB7 are control data. LCD_RW_WR : Read / Write execution control Pin. In 6800 Mode, High : Read, Low : Write. In 8080 Mode, Write enable sognal. LCD_E_RD : Read / Write execution control Pin. In 6800 Mode, Read / Write Enable signal. In 8080 Mode, Read enable signal. DB[3:0] : Bi-directional data bus low 4bits. DB[5:4] : Bi-directional data bus data[5:4] bit & data[1:0] bit at 4bit mode. DB[6] : Bi-directional data bus data[6], data[2] at Parallel Mode, clock(SCLK) at serial mode. DB[7] : Bi-directional data bus data[7], data[3] at Parallel Mode, serial output data(SDO) at serial mode. serial
TIMING DIAGRAM
6800 Mode RS RW CSB E DB_W DB_R
8080 Mode RS /RD /WR CSB DB_W DB_R
Serial Mode SCLK CSB
RS SDO
REGISTERS
Name LCD_CON LCD_WCMD LCD_WDATA LCD_RCMD LCD_RDATA LCD_DBUFF LCD_INTCON LCD_STATUS LCD_PHTIME Width 32 32 32 32 32 32 32 32 32 Address 0xhhhh 0000 0xhhhh 0004 0xhhhh 0008 0xhhhh 000C 0xhhhh 0010 0xhhhh 0014 0xhhhh 0018 0xhhhh 001C 0xhhhh 0020 R/W R/W W W W W R Description Control register. Write command register. Write data register Read command register. Read data register. Read Data buffer Rest Value 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0066
R/W Interrupt control register R LCD Interface status
R/W Phase time register
LCD_CON
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit 9 8:7
Name LCD_ON W_LEN
Type Description R/W R/W LCD Interface On. APB Bus interface word length. 00 : 8 bit. 01 : 16 bit 10 : 32 bit
Reset Value 0 00
6
ENDIAN
R/W
APB Bus word Endian. 0 : Little endian. 1 : Big endian. When W_LEN = 0, No effect.
0
5
PS1
R/W
Microprocessor interface select. When PS0 = 0 PS1 = 0 : 3 pin-SPI MPU interface. PS1 = 1 : 4 pin-SPI MPU interface. When PS0 = 1
0
PS1 = 0 : 8080-series parallel MPU interface. PS2 = 1 : 6800-series parallel MPU interface. 4 PS0 R/W Parallel/serial data select. When 0 Serial MPU Interface. When 1 Parallel MPU interface. 3 BUS_M R/W Bus mode Select at parallel Interface. BUS_M = 0 : 8bit Data Bus. BUS_M = 1 : 4 bit Data Bus. 2:0 CLK_SEL R/W LCD clock select. 000 : PCLK / 1, 010 : PCLK / 4, 001 : PCLK / 2 011 : PCLK / 8 0 0 0
100 : PCLK / 16, 101 : PCLK / 32 110 : PCLK / 64, 111 : PCLK / 128
LCD_WCMD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit 7:0
Name WCMD
Type W
Description Write LCD driver command.
Rest Value 0x000
LCD_WDATA
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit 31:0
*
Name WDATA
Type W
Description Write LCD driver data.
Rest Value 0x000
Note : In 8bit Length mode, 31~ 8 data bits are not valid.
LCD_RCMD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit 7:0
Name RCMD
Type W
Description Read command LCD driver command. ] Dummy value.
Rest Value 0x000
LCD_RDATA 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit 7:0
Name RDATA
Type W
Description Read command LCD driver data. Dummy value.
Rest Value 0x000
LCD_DBUFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit 7:0
Name DBUFF
Type W
Description Read LCD driver data buff.
Rest Value 0x000
LCD_STATUS 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit 7 6 5 4 3 2 1 0
Name Interrupt Reserved OW FULL HFULL HEMPTY EMPTY READON
Type Description R R R R R R R R FIFO is Over write. FIFO is Full. FIFO is half full. FIFO is half empty. FIFO is empty. Read operation done. Interrupt Flag.
Rest Value 0 0 0 0 0
0 1
LCD_INT_CON 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit 7 6 5 4
Name INT_EN
Type Description R/W Interrupt enable. FIFO Clear. Over write interrupt enable. FIFO Full interrupt enable.
Rest Value 0 0 0 0
F_CLEAR R/W OW_EN F_EN R/W R/W
3 2 1 0
HF_EN HE_EN EM_EN RED_EN
R/W R/W R/W R/W
FIFO half full interrupt enable. FIFO half empty interrupt enable. FIFO empty interrupt enable. Read done interrupt enable.
0 0 0 0
LCD_PHTIME 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit 7:4 3:0
Name
Type Description Phase 1 time register Phase 1 time register
Rest Value 6 0
PH1_TIME R/W PH2_TIME R/W
OPERATION
- Clock Select
As to the operation frequency of LCD Driver IC, CPU selects the frequency of clock in LCD interface controller. There is the register for this operation. Using this internal clock, The following signals, RD_RW, E_RD and CSB are generated. At this time, the high pulse width(tPWH ) and the low pulse width (tPWL) is controlled also by LCD_PHTIME Registe.
PCLK 100 MHz
CLK_SEL 000 ( x 1 ) 001 ( x 1/2) 010 ( x 1/4) 011 ( x 1/8) 100 ( x 1/16) 101 ( x 1/32) 110 (x 1/64) 111 ( x 1/128)
tPW time unit (ns) 10 20 40 80 160 320 640 1280 20 40 -1280 2560
50 MHz
000 ( x 1 ) 001 ( x 1/2) -110 ( x 1/64) 111 ( x 1/128)
tPW = (PH1_TIME Value + 1) x tPW time unit (Phase 1) tPW = (PH2_TIME Value + 1) x tPW time unit (Phase 2)
- Mode Select The bit PS1 and PS0 of control register set the Interface mode.
PS0
PS1
Interface Mode
Data /instruction None
Data
Read/Write
Serial Clock
0
0
Serial (3 pin)
SDO(DB7)
Write only
SCLK(DB6)
0
1
Serial (4 pin)
RS
SDO(DB7)
Write only
SCLK(DB6)
1
0
Parallel (8080)
RS
DB[7:0]
Read : E_RD Write : RW_WR
None
1
1
Parallel (6800)
RS
DB[7:0]
Read : RW_WR = high Write : RW_WR = low
None
In parallel Interface mode, using the BUS_M bit of control register, 8bit data bus mode or 4bit data bus mode is set.
- Interrupt Control There are 5 Interrupt sources as the following: 1) Read done 2) FIFO empty 3) FIFO Half empty 4) FIFO Full 5) FIFO Over run Each interrupt source can be masked each maskable control bit or common interrupt mask bit. If the Interrupt is occurred at once, CPU can find out the source by reading status register. The way of clearing each interrupt source is as following: 1) FIFO empty or FIFO Half empty: Writing the data to FIFO. 2) FIFO Full or FIFO Over run: clearing FIFO 3) Read done : reading LCD_DBUFF register.
- LCD Command & Data The bit position 7 in FIFO named RS bit is used as indiacating the data or command. This value is set automatically as to writing to which register. To write command to LCD Driver, CPU have to write to LCD_WCMD. At this time, The value of RS is set automatically as zero. LCD interfase controller outputs the command to LCD Driver IC. To write data to LCD Driver, CPU has to write to LCD_WDATA. At this time, the value of RS is set automatically as one. LCD interface controller outputs the data to LCD Driver IC. To read the status of LCD Driver, CPU writes the dummy data to LCD_RCMD register.
Then, The status value is saved in LCD_DBUFF. To read the data of LCD Driver, CPU writes the dummy data to LCD_RDAT register. Then, The status value is saved in LCD_DBUFF. After reading the status or data is finished, the read_done_flag is set to high. CPU read this value using interrupt or polling.


▲Up To Search▲   

 
Price & Availability of S5L840F

All Rights Reserved © IC-ON-LINE 2003 - 2022  

[Add Bookmark] [Contact Us] [Link exchange] [Privacy policy]
Mirror Sites :  [www.datasheet.hk]   [www.maxim4u.com]  [www.ic-on-line.cn] [www.ic-on-line.com] [www.ic-on-line.net] [www.alldatasheet.com.cn] [www.gdcy.com]  [www.gdcy.net]


 . . . . .
  We use cookies to deliver the best possible web experience and assist with our advertising efforts. By continuing to use this site, you consent to the use of cookies. For more information on cookies, please take a look at our Privacy Policy. X